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POWER CONSCIOUS TESTING
BONHOMME Y, GIRARD P, LANDRAULT C.,
PRA VOSSOUDOVITCH S.
LIRMM - Laboratoire d’Informatique de Robotique et de Microftlectronique de Montpellier, University Montpellier II / CNRS, 161 rue Ada, 34392 Montpellier Cedex 5 France
E-mail: <name>@lirmm.frURL :http://www.lirmm.fr/~w3mic
Abstract. Test power relates to the power consumed during test of integrated circuits or embedded cores. Test power is now a big concern in large System-on-Chip designs. In this paper, we propose to shortly review the state-of-the-art in this domain. We first survey the recent approaches proposed for minimizing test power. Next, we propose some interesting directions for the development of new low power testing techniques by enumerating the relevant criteria that have to be satisfied.
1. Introduction
The System-on-Chip (SOC) revolution has brought some new challenges to both design and test engineers. Among these challenges, power dissipation is one of the important issues [ 1]. Generally, a circuit may consume more power in the test mode than in the normal mode [2]. It has been shown in
[3] that the test power can be as high as twice the power consumed in the normal mode. There are several reasons for this increased test power. First, the test efficiency has been shown to have a high correlation with the toggle rate; hence in the test mode, the switching activity of all nodes is often several times higher than the activity during normal operations. Secondly, in a SOC, parallel testing is frequently employed with the aim to reduce the test application time; this may result in excessive energy and power dissipation. Third, the design-for-testability (DfT) circuitry embedded in a circuit to reduce the test complexity is often idle during normal operations but may be intensively used in the test mode. Another reason is that successive functional input vectors applied to a given circuit during system mode have a significant correlation, while the correlation between consecutive test patterns can be very low [4]. This can cause significantly larger switching activity in the circuit during test than that during its normal operation. Since power dissipation in CMOS circuits is proportional to switching activity, this excessive switching activity during test may be responsible for cost, reliability, performance verification, autonomy and technology related problems [5]. For example, in battery-powered devices, the power consumed during application of power-up or periodical on-line tests, which are often implemented resorting to the Built-In Self Test (BIST) approach, can dramatically shorten the battery lifetime. Another example of such problems is that increased circuit activity and hence power consumption leads to increased current flows during test, making the use of expensive packages for the removal of excessive heat an imperative need. Increased heat leads also to serious silicon failure mechanisms, such as electro-migration, that reduce the reliability of a system operating under such conditions. A detailed description of these problems is proposed in [5].
2. Terminology
As discussed earlier, one of the current concerns, which may turn into a major engineering problem in the future of SOC development, is test power [6]. As both the SOC designs and the deep-submicron geometry become prevalent, the hugeness of designs, the tightening of timing constraints, the rising of frequencies, and the lowering of applied voltages all affect the power consumption systems of silicon devices [7]. These concerns involve energy, average power, peak power, instantaneous power and thermal overload. Below are some definitions.
Energy: the total switching activity generated during test application. Energy has impact on the battery lifetime during power up or periodic self-test of battery operated devices.
Average Power: the total distribution of power over a time period, which is generally the amount of power consumed during the application of a test. The average power is given by the ratio between the energy and the test time. Elevated average power adds to the thermal load that must be vented away from the device under test. It may cause structural damage to the silicon (hot spots), to bonding wires or to the package.
Peak Power: the highest value of power at any given instant. The peak power determines the thermal and electrical limits of components and the system packaging requirements. If the peak power exceeds a certain limit, the correct functioning of the entire circuit is no longer guaranteed. - In fact, the time window for the definition of the peak power is related to the thermal capacity of the chip, and forcing this window to one clock period is sometimes just a simplifying assumption. For example, if the circuit has a peak power consumption during only one cycle but it has power consumption within the limit of thermal capacity of the chip for all other cycles, the circuit will not be damaged because the energy consumed, which corresponds to the peak power consumption times one cycle, will not be enough to elevate chip temperature over the limit of thermal capacity of the chip (unless the peak power consumption is far higher than normal power consumption). In order to damage the chip, high (not only highest) power consumption should last for several cycles to consume enough energy that can elevate chip temperature over the limit.
3. Related work on test power
Until now, a number of ad hoc solutions have been practiced in industry for considering power consumption during test. These solutions consist in over-sizing power supply, package and cooling to stand the increased current during testing, or reducing the test operation frequency. Unfortunately, these solutions increase either hardware costs or test time, and may lead to a loss of defect coverage as dynamic faults may be masked. Thereby, a number of novel solutions have been propo sed to cope with the power and energy problems during test. These approaches can be classified as follows:
1) TestScheduling Algorithms [3,8,29,30,31,35,38]. The goal in these approaches is to determine the blocks of a complex SOC design to be activated in parallel at each stage of the test session in order to reduce the number of concurrently tested modules. The average test power is reduced and consequently, the temperature related problems avoided by the increase of the test time duration.
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2) Vector Filtering BIST Techniques [9,10]. As each vector applied to the CUT consumes power but not every vector generated by the pseudo-random TPG contributes to the final fault coverage, the vector filtering architectures consist in preventing application of non-detecting vectors to the CUT. This approach is very effective in reducing average test power without reducing fault coverage.
3) Low Power BIST Test Pattern Generators [4,11-14]. TPGs based either on LFSRs or Cellular Automata (CA) are carefully designed to reduce the activity at circuit inputs, thus reducing power consumption. These approaches effectively reduce test power but sometimes at a cost of sub-optimal fault coverage.
4) Circuit Partitioning Techniques for BIST [15]. This approach consists in partitioning the original circuit into structural sub-circuits so that each sub-circuit can be successively tested through different BIST sessions. The average power, the peak power and the energy consumption during BIST are minimized at a low expense of area overhead and with no loss of fault coverage.
5) Low Power ATPGAlgorithms [16-18]. New ATPGs are proposed with the intent of generating test patterns able to reduce test power in addition to the classical ATPG objectives (fault coverage and test length).
6) Vector or Scan Latch Ordering Techniques [1921,32,33,34,36,37,40]. These are techniques in which the switching activity of a CUT is reduced by modifying either the order in which test vectors of a given test sequence are applied to this CUT, or the order in which the scan flip-flops are chained to form the shift register, or the way according which Xs in test vectors are assigned to 0 or 1. These techniques are normally usable during ATE testing.
7) Static Compaction and Input Control Techniques [22,23]. The goal of these techniques is to minimize the scan vector power dissipation. This is done by either appropriately compacting test vectors of a test sequence, or by applying a specific blocking vector at the beginning of each scan shifting operation.
8) Scan Path Modification Techniques [24-26]. These techniques propose to modify the scan architecture in such a way that the switching activity in the CUT is minimized during scan shifting operations. This is accomplished by either adding delay buffers among the scan chains [24], or by segmenting the original scan chains into several sub-scan chains [25,26].
9) Clock Scheme Modification Techniques [27,28,39,41]. These techniques consist in modifying the clock scheme connected to the CUT and/or to the scan chains to either partially disable the clock signal, or to reduce the clock rate during the test session without increasing the test time. In certain cases this technique is improved by rearranging the test vectors.
4. Discussion
As can be observed, the number and the diversity of the available techniques are quite important, and hence the selection of one of them by a designer or a test engineer who is interested in implementing such a technique depends on a number ofparameters. Obviously, the first one is the context in which the technique has to be implemented; external
testing, scan testing, scan-BIST, parallel BIST, ... will lead to completely different choices. For example, a test vector ordering technique can be utilized during ATE or scan testing, but cannot be used in a BIST situation where vectors’ order is firmly defined by the generator. The second parameter concerns the way we want to act on the test power minimization; do we want to act on the test sequence or on the test architecture ? In the first case, we will select test vector ordering or compaction techniques (for ATE or scan testing). In the second case, we will prefer techniques as those presented in [25,26,27]. The third parameter is the possibility a designer or a test engineer has to relax some of the classical test constraints when implementing such a low power testing technique. Actually, there is a number of relevant criteria that must be considered when selecting solutions for minimizing test power. Fault coverage and test time, which are among the main test constraints, have to be unaltered by the implemented technique. The area overhead due to hardware modifications must be acceptably low [33]. The circuit performances have to be maintained. The impact on the design flow, and hence on the design time, must be low enough for the solution to be acceptable. Consequently, according to the importance attached by the designer or test engineer to each one of these constraints, the selection of a low power testing technique among the available ones will be different. This is due to the fact that the existing techniques, although they all minimize test power, have a different impact on the above criteria. For example, the test scheduling technique proposed in [3] for test power reduction during BIST will be used in situations where the test time is not a crucial test criterion. On the other side, techniques as those presented in [13,28] will be preferred if the test time has to be unmodified.
In addition to the above mentioned selection criteria, one of the most important point a designer or a test engineer has to take into account when selecting a solution for minimizing test power is the clock power. Results in [6] suggest that the clock power, which is the power dissipated in the clock tree each time the clock makes a transition, is a significant component of the total power during test. In some cases, it may dominate the logic power dissipated when logic gates in the circuit switch. For this reason, special care must be taken to the clock power. This means that the clock tree has to be designed as small as possible, or that clock signals can be disabled as often as possible as it is the case in traditional low-power systems.
References: 1. Crouch A. Design-for-Test for Digital IC’s and Embedded Core Systems // Prentice Hall, 1999. 2. Bushnell M.L., Agrawal V.D. Essentials ofElectronic Testing // Kluwer Academic Publishers, Boston, 2000. 3. Zorian Y. A Distributed BIST Control Scheme for Complex VLSI Devices // IEEE VLSI T est Symposium. May 1993. PP. 4-9. 4. WangS., GuptaS. DS-LFSR : A New BIST TPG for Low Heat Dissipation // IEEE International Test Conference. November 1997. PP. 848-857. 5. GirardP. Low Power Testing of VLSI Circuits: Problems and Solutions // IEEE International Symposium on Quality ofElectronic Design. March 2000. PP. 173179. 6. Pouya B., Crouch A. Optimization Trade-offs for Vector Volume and Test Power // IEEE International Test Conference. October2000. PP. 873-881.7. PedramM. Power Minimization IC Design : Principles and Applications // ACM Trans. on Design Auto. ofElectronic Systems, 1996. Vol. 1, no. 1. PP. 3-56. 8. Chou R.M., Saluja K.K., Agrawal V.D. Power Constraint Scheduling of Tests // IEEE International Conference on VLSI Design, 1994. PP. 271-274. GirardP., GuillerL., Landrault C., Pravossoudovitch
30
R&I, 2003, N 3
S. A Test Vector Inhibiting Technique for Low Energy BIST Design // IEEE VLSI Test Symposium. May 1999. PP. 407-412. 10. Gerstend^fer S., WunderlichH.J. Minimized Power Consumption for Scan-based BIST // IEEE International Test Conference. September 1999. PP. 77-84. 11. WangS., Gupta S.K. LT-RTPG: A New Test-Per-Scan BIST TPG for Low Heat Dissipation // IEEE International Test Conference. September 1999. PP. 85-94. 12. ZhangX., Roy K., BhawmikS. POWERTEST : A Tool for Energy Conscious Weighted Random Pattern Testing //IEEE International Conference on VLSI Design, 1999. 13. Corno F., Rebaudengo M., SonzaReordaM., Squillero G., ViolenteM. Low Power BIST via Non-Linear Hybrid Cellular Automata // IEEE VLSI Test Symposium, May 2000. PP. 29-34. 14. GizopoulosD., KranitisN., PaschalisA., Psarakis M., Zorian Y. Low Power/Energy BIST Scheme for Datapaths // IEEE VLSI Test Symposium. May 2000. PP. 23-28. 15. Girard P., GuillerL., Landrault C., Pravossoudovitch S. Low Power BIST Design by Hypergraph Partitioning: Methodology and Architectures // IEEE International Test Conference. October2000. PP. 652-661. 16. Wang S., Gupta S.K. ATPG for Heat Dissipation Minimization During Test Application // IEEE International Test Conference, October 1994. PP. 250-258. 17. WangS., Gupta S.K. ATPG for Heat Dissipation Minimization for Scan T esting // ACM/ IEEE Design Automation Conference, pp. 614-619, June 1997. 18. Corno F., Prinetto P., Rebaudengo M., Sonza Reorda M. A Test Pattern Generation Methodology for Low Power Consumption // IEEE VLSI Test Symposium, May 1998. PP. 453-459. 19. DabholkarV., Chakravarty S., Pomeranz I., Reddy S.M. Techniques for Reducing Power Dissipation During Test Application in Full Scan Circuits // IEEE Transactions on CAD, December 1998. Vol. 17, N° 12. PP. 1325-1333. 20. Girard P, Landrault C., Pravossoudovitch S., Severac D. Reducing Power Consumption during Test Application by Test Vector Ordering // IEEE International Symposium on Circuits and Systems, CD-Rom proceedings, June 1998. 21. GirardP., Guiller L., Landrault C., Pravossoudovitch S. A Test Vector Ordering Technique for Switching Activity Reduction during Test Operation // IEEE Great Lakes Symposium on VLSI, March 1999. PP. 24-27. 22. SankaralingamR., Oruganti R'., ToubaN. Static Compaction Techniques to Control Scan Vector Power Dissipation // IEEE VLSI Test Symposium, May 2000. PP. 35-42. 23. Huang T.C., Lee K.J. An Input Control Technique for Power Reduction in Scan Circuits During Test Application // IEEE Asian Test Symposium, November 1999. PP. 315-320. 24. Lee K-J., Huang T-C., Chen J-J. Peak-PowerReduction for Multiple-Scan Circuits during Test Application // IEEE Asian Test Symposium. December 2000. PP. 453-458. 25. Whetsel L. Adapting Scan Architectures for Low Power Operation // IEEE International T est
Conference. October2000. PP. 863-872. 26.Bonhomme Y., Girard P., Guiller L., Landrault C., Pravossoudovitch S. A Gated Clock Scheme for Low Power Scan Testing of Logic ICs or Embedded Cores // IEEE Asian Test Symposium. November 2001. PP. 253258.27. SankaralingamR.,PouyaB., ToubaN.A. Reducing Power Dissipation During Test Using Scan Chain Disable // IEEE VLSI Test Symposium. May 2001. PP. 319-324. 28. GirardP., Guiller L., Landrault C., Pravossoudovitch S., Wunderlich H.J. A Modified Clock Scheme for a LowPower BIST Test Pattern Generator // IEEE VLSI Test Symposium. May 2001. PP. 306-311.29. Larsson E., Peng Z. Test Scheduling and Scan-Chain Division under Power Constraints // IEEE Asian Test Symposium. December 2001. PP. 259-264. 30.Huang Y. etal. Optimal Core Wrapper Width Selection and SOC Test Scheduling Based on 3D Packing Algorithm // IEEE International Test Conference. October2002. PP. 74-82. 31. Iyengar V., ChakrabartyK., MarinissenE.J. Integrated Wrapper/TAM CoOptimization, Constraint-Driven Test Scheduling, and Tester Data Volume Reduction for SOCs // Design Automation Conference. June 2002. PP. 685-690. 32. Bonhomme Y., GirardP., Landrault C., Pravossoudovitch S. Power Driven Chaining of Flip-flops in Scan Architectures // IEEE International Test Conference. October
2002. PP. 796-803. 33. Bonhomme Y., GirardP., Landrault C., Pravossoudovitch S. Efficient Scan Chain Design for Power Minimization During Scan Testing Under Routing Constraint // IEEE International Test Conference, to appear, September-October
2003. 34. Sinanoglu O., Bayraktaroglu I., Orailoglu A. Dynamic Test Data T ransformations for Average and Peak Power Reductions // IEEE European Test Workshop. June 2002. PP. 113-118. 35. Larsson E., Fujiwara H. Power Constrained Preemptive TAM Scheduling // IEEE European Test Workshop. June 2002. PP. 119126. 36. Sankaralingam R., Touba N. Controlling Peak Power during Scan Testing // IEEE VLSI Test Symposium. May 2002. PP. 153-159. 37. Kajihara S., Ishida K., Miyase K. Test Vector Modification for Power Reduction during Scan Testing // IEEE VLSI Test Symposium. May 2002. PP.160-165. 38. Schuele T., Stroele B. Test Scheduling for Minimal Energy Consumption under Power Constraints // IEEE VLSI Test Symposium. May 2001. PP. 312318. 39. Sankaralingam R., Pouya B., Touba N. Reducing Power Dissipation During Test Using Scan Chain Disable // IEEE VLSI Test Symposium. May2001. PP. 319-324. 40. Higami Y., Kobayashi S.-Y., Takamatsu Y. A method to Reduce Power Dissipation during Test for Sequential Circuits // IEEE Asian Test Symposium, pp. 326-331, November 2002. 41. LeeK.-J., Chen J.-J. Reducing Test Application Time and Power Dissipation for Scan-Based Testing via Multiple Clock Disabling // IEEE Asian Test Symposium. November 2002. PP. 338-343.
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