Научная статья на тему 'Observability estimation of a state variable when the los technique is applied'

Observability estimation of a state variable when the los technique is applied Текст научной статьи по специальности «Математика»

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Ключевые слова
PATH DELAY FAULT (PDF) / EQUIVALENT NORMAL FORM (ENF) / LAUNCH-ON-SHIFT (LOS) SCAN TECHNIQUE / НЕИСПРАВНОСТЬ ЗАДЕРЖКИ ПУТИ / РОБАСТНАЯ НЕИСПРАВНОСТЬ ЗАДЕРЖКИ / ЭКВИВАЛЕНТНАЯ НОРМАЛЬНАЯ ФОРМА (ЭНФ) / LOS-ТЕХНИКА СКАНИРОВАНИЯ СОСТОЯНИЙ СХЕМЫ / ROBUST PDF

Аннотация научной статьи по математике, автор научной работы — Melnikov Alexey Vladimirovich

Structural scan based delay testing is used for detecting the circuit delays. Because of architectural limitations not an each test pair can be applied through a scan delay test. Enhanced scan techniques were developed to remove these restrictions on vector pairs. Unfortunately these techniques have rarely been used in practice because of the near doubling of the flip-flop area. Most promising are partial enhanced scan approaches based on partial selection of flip-flops for including them in enhanced scan chains. The problem is how to select proper flip-flops. In this paper we suggest to estimate flip-flop observability as a probability of robust PDF manifestation for paths connected with corresponding state variable in the frame of the LOS technique. It is desirable to include in enhanced scan chains flip-flops with low observabilities of corresponding state variables. The algorithm of observability calculation is developed and experimental results are presented.

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Текст научной работы на тему «Observability estimation of a state variable when the los technique is applied»

ВЕСТНИК ТОМСКОГО ГОСУДАРСТВЕННОГО УНИВЕРСИТЕТА

2012 Управление, вычислительная техника и информатика № 3(20)

УДК 004.052.32

A.V. Melnikov

OBSERVABILITY ESTIMATION OF A STATE VARIABLE WHEN THE LOS TECHNIQUE IS APPLIED1

Structural scan based delay testing is used for detecting the circuit delays. Because of architectural limitations not an each test pair can be applied through a scan delay test. Enhanced scan techniques were developed to remove these restrictions on vector pairs. Unfortunately these techniques have rarely been used in practice because of the near doubling of the flip-flop area. Most promising are partial enhanced scan approaches based on partial selection of flip-flops for including them in enhanced scan chains. The problem is how to select proper flip-flops. In this paper we suggest to estimate flip-flop observability as a probability of robust PDF manifestation for paths connected with corresponding state variable in the frame of the LOS technique. It is desirable to include in enhanced scan chains flip-flops with low observabilities of corresponding state variables. The algorithm of observability calculation is developed and experimental results are presented.

Keywords: path delay fault (PDF); robust PDF; equivalent normal form (ENF); Launch-on-Shift (LOS) scan technique.

Because of architectural limitations not an each test pair vb v2 can be applied through a scan delay test. Enhanced scan techniques were developed to remove these restrictions on vector pairs. Unfortunately these techniques have rarely been used in practice because of the near doubling of the flip-flop area. Most promising are partial enhanced scan approaches based on proper selection of flip-flops for including them in enhanced scan chains [1].

In the paper [2] it was suggested to include flip-flops with low estimations of controllability of corresponding state variables in scan chains. Facilities of signal change propagation from an input to an output of a circuit (observability) are not considered. In the paper [3] estimations oriented to cutting the test length and improving the test coverage were developed for both controllability and observability. In both papers estimations are related to providing the constant value for the state variable but not to providing the change of its value.

1. Calculation of observability estimation of a state variable

Suppose we have a synchronous circuit (Fig. 1) in which x1,...,xn are input variables, yb... ,yp are state variables, zb... ,zm are output variables, and d1,.,dp are flip-flops. Circuit C is a combinational part of a sequential circuit.

Random input sequence of a sequential circuit is described with a probability distribution p(x1),. ,p(xn). Here p(xi), i = 1,...,n, is a probability an input variable xi takes the 1 value on a random input vector. Assume that a probability distribution p(y1),. ,p(yp) of state variables is also known.

The problem of probability calculation of robust PDF manifestation (calculation of observability estimation) for the state variable was considered in the paper [4] under

1This work was supported by grant «РФФИ № 11-08-92694-ИНД».

suggestion that the vector vi of the test pair is a unit of random sequence with the given probability distribution of i values of input and state variables. Moreover each test pair vi, v2 can be applied through a delay test. The algorithm of observability estimation is based on deriving a ROBDD representation of all robust PDF test pairs for the path. Remind that ROBDD paths from its root to the i value terminal node represent a Disjoint Sum of Products (DSoP). In a DSoP all products are pairwise orthogonal. When the LOS technique is applied we also consider that the vector vi in the test pair is a unit of the random

sequence but the vector v2 is obtained by single right

cyclic shift among state variables of the vector v1. The latter means that not an each test pair vi, v2 can be applied in the frame of the LOS technique. In that case we first suggest deriving a ROBDD representation of all robust PDF test pairs for each product (of the Equivalent Normal Form) that generates test pairs. Then we derive prime products for each function represented by a ROBDD. After that we correct prime products in order to provide existence of test pairs in the frame of the LOS technique.

Consider ENF products containing the literal representing the path a. In line with theorems i, 2 [4] such products may originate robust PDF test pairs. Find all robust test pairs both for rising and falling transitions of the given path originated by one product of ENF [4]. For that we have to find product K that does not contain repeated variable Xi. Analyzing ENF we don’t pay attention to index sequences of literals representing paths of the circuit. All roots of the special equation [4] D = 0 are represented as ROBDD R. R is compact description of a disjoint sum of products (DSoP). Exclude the variable xt from K and obtain the product K*. Represent the expression K*&DSoP as

ROBDD R*. Each path of R* from the root till the i terminal node represents the

product corresponding to 2”-r_i robust test pairs consisting of neighboring Boolean vectors. Here r is a rank of the product originated by the R* path and n is the number of ENF variables.

Extract from the R* sum of all prime products and denote it as a SoPP. Any product of the SoPP represents conditions for forming test pairs: each test pair must have same values a) among variables of K* (theorems i, 2, point 4, [4]) and b) among subset of the rest variables (except xi) which provide orthogonality to products of the set K (theorems

i, 2, point 3[4]). Notice that all minimal subsets are represented with prime products of the SoPP and we need them all in order to keep all test pairs. Experimental results showed that SoPPs as a rule are rather simple.

Let Kj be the product of the SoPP. Consider the following proposals.

Proposal 1. Product Kj from the SoPP with literals ykyk+i (ykyk+i), k^i-i, does

not originate robust test pairs (if k = n, then k+i = i).

Proof. Really both vectors vi, v2 must turn the product Kj into the i but it is impossible if the Kj contains literals ykyk+i (ykyk+i), k^i-i, as v2 is obtained from vi by single right cyclic shift among state variables. The proposal is proved.

Proposal 2. The product Kj from the SoPP with literals yi-iy+i (yi-iy+i) does not originate robust test pairs. If i = n we should consider literals yn-i yi (yn_iyi), if i = i -literals yny2 (yny2).

-> zi

Fig. i. Synchronous circuit

m

Proof. Really both vectors vi, v2 must turn the product Kj into the i and at the same time provide the value change of the variable yi. But it is impossible if the Kj contains above mentioned literals as v2 is obtained from vi by single right cyclic shift among state variables. The proposal is proved.

If a product K* in accordance with proposals i and 2 does not originate robust test pairs it must be excluded from the consideration. Consider K* that may originate robust test pairs.

Find the proper R* and the SoPP. Exclude from the SoPP products which don’t originate robust test pairs. Denote the result as the SoPP*. Consider the SoPP* and find all test pairs originated by these products when the LOS technique is used. Represent them as a ROBDD R(Kj). For that we have to do the following.

1. If a literal yk-i is absent in the Kj from the SoPP* but a literal yk is present, k^i, k-i^i then add the literal yk-i into the Kj so that signs of inversions of both these literals are the same (if k = i, then k - i = n). This procedure provides turning the product Kj into the i by both vectors vi, v2 when the LOS technique is used.

Recall that any product Kj does not contain the variable yi. Add this variable to generate robust test pair providing the state variable value change.

2. If variables yi-i, yi+i are both present in the Kj add the variable yt with the same sign of inversion that the variable yi+i has.

3. If the variable yi+i is present in the Kj but yi-i is absent add the variable yi with the same sign of inversion that the variable yi+i has and add yi-i with the opposite sign of inversion.

4. If the variable yi+i is absent in the Kj but yi-i is present add variables y, yi+i with the opposite sign of inversion that the variable yI-i has.

5. If variables yi-i, yi+i are absent in the product Kj we generate two products from the Kj. One is obtained by appending yi yi+i without an inversion and the variable yi-i with an inversion. Another one by appending yi yM with an inversion and yI-i without an inversion.

If i = n (i = i) the similar 2-5 conditions may be formulated for variables yn-i, yi (yn, y2).

Points 2-5 provide conditions for turning the product Kj into the i on vectors vi, v2 and for the value change of the state variable yi in the test pair. After executing points i-5 for all products of the SoPP* we obtain the SoP*. We should additionally check products of the SoP* against proposals i, 2, because of boundary conditions may not be satisfied after appending some variables in points i-5. After exclusion some incompatible products we obtain SoP**. Its products may not be prime products but each of them provides generation of robust test pairs which turns into the i corresponding product of the SoPP*.

Execute disjunction of all SoPs** corresponding to different ENF products related to the path a and represent this disjunction as a ROBDD Ra.

It should be noted that in special case, when n<3 (number of state variables is less than or equal to 3) all observabilities are equal to 0 because of incompatibility with proposals i, 2.

Theorem 1. When using the LOS technique the robust test pair exists if and only if the vector vi is absorbed with a product contained in the ROBDD Ra.

Proof. Let the vector vi be absorbed with one product K from the DSoP corresponding to the Ra. Show that vi forms the robust test pair when the LOS technique

is used. From the construction of the DSoP we conclude that the variable y changes its value to opposite one on the vector v2. As the K is absorbed by at least one product from the SoPP* (proper K) then vectors v1, v2 keep values of variables of the product K* (theorems 1, 2, point 4) and vectors v1, v2 are orthogonal to the set K (theorems 1, 2, point 3). It means that v1 and v2 form robust PDF test pair together.

Let we have the robust test pair so that the vector v2 is built in the frame of the LOS technique. Show that the vector v1 of this test pair is absorbed with a product from the DSoP corresponding to the Ra. The construction of the ROBDD corresponding to the Ra let us forming v2 from any possible v1: we have in the proper SoP** all necessary minimal subsets of variables for providing the orthogonality to products of the set K. The ROBDD Ra contains functions represented by all necessary SoPs** and consequently v1 is absorbed with a product of the DSoP of the Ra. The theorem is proved.

Using Ra and the probability distribution of input and state variables we may calculate a probability of the robust PDF manifestation (observability estimation) along the path a.

We can calculate observability estimation P0(LOS) of the state variable y for one circuit output by deriving ROBDDs for each path started at y and terminated at this circuit output. For that we must summarize observability estimations for each path corresponding to the state variable and the circuit output as products representing test pairs for different paths terminated at one output are orthogonal.

To obtain more representative results we should calculate average observability estimation Poavg(LOS) of the state variable y ,■ per all circuit outputs. In the similar way it is possible to calculate observability estimations for all state variables of the sequential circuit. We have got the following experimental results.

2. Experimental results

The suggested approach is based on ENF analysis and ROBDD application. ENF is very complicate formula for real circuits. It is possible to use OR-AND trees to present all paths of a circuit C [5], one OR-AND tree for each output of a combinational part of a sequential circuit. These trees were used for finding estimations for benchmarks of the Table.

Experimental results of observability estimations for ISCAS89 benchmarks set

Circuit Inputs Outputs State Variables Po,ara(LOS)*10000

s208 11 2 Y 8; Y 7; Y 4; Y 3; Y 2; Y 1; Y 6; Y 5 0; 0; 21; 25; 20; 53; 0; 4;

s298 3 6 G18; G14; G12; G10; G11; G13; G23; G22; G15; G20; G16; G19; G21; G17 0; 41; 24; 51; 14; 27; 83; 63; 62; 0; 4; 0; 4; 0;

s344 9 11 ACVQN0; CT0; CT1; CT2; MRVQN0; MRVQN1; MRVQN2; MRVQN3; AX0; AX1; ACVQN1; AX2; ACVQN2; AX3; ACVQN3 11; 110; 24; 52; 2; 24; 12; 24; 43; 42; 5; 48; 7; 49; 10;

s349 9 11 CT2; CT0; CT1; MRVQN0; MRVQN1; MRVQN2; MRVQN3; AX0; ACVQN0; AX1; ACVQN1; AX2; ACVQN2; AX3; ACVQN3 75; 52; 6; 2; 24; 24; 24; 39; 12; 42; 5; 42; 5; 48; 5;

Table continued

Circuit

Inputs

Outputs

State Variables

P0,aTO(LOSH0000

s382

6

OLATCH_G1L; C3_Q2; UC_17; UC_9; UC_10;

UC_11; UC_8; TESTL;

UC_18; UC_19; UC_16; C3_Q1; C3_Q0; C3_Q3; FML; OLATCH_FEL;

OLATCH_G2L;

OLATCH_R1 L;

OLATCH_Y2L; OLATCHVUC_5; OLATCHVUC 6

0; 28;

25; 6; 0;

18; 7; 51;

2; 9; 6;

15; 21; 18; 46; 32;

0;

0; 0;

0 0

s386

v7; v9; v8; v10; v12; v11

0; 6; 0; 54; 0; 2

s400

OLATCH_G2L; OLATCH_FEL; FML; C3_Q3; TESTL; UC_8; UC_9; UC_10; UC_11; UC_16; UC_17; UC_18; UC_19; C3_Q2; C3_Q1; C3_Q0; OLATCH_Y2L; OLATCHVUC_5; OLATCH_G1L; OLATCHVUC_6;

OLATCH R1L

0;

33; 46; 23; 48; 4; 6; 0; 18; 4; 23; 2; 9; 25; 15; 29;

0;

0 0 0 0

; G24; G19; G22; G20; 0; 41; 16; 17; 16;

; G15; G31; G14; G11; 6; 3; 46; 2; 3;

; G13; G16; G17; G21; 6; 17; 9; 24; 27;

; G29; G25; G28; G30; 46 ; 0; 0; 0; 0;

s444

G27

G18

G12

G23

G26

s510

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19

st_0; st_1; st_3; st_4; st_5; st 2

0; 0; 0; 24; 24; 24

s526

G25

G14

G18

G22

G24

; G13; G19; G11; G10;

; G15; G16; G30; G17;

; G12; G21; G20; G29;

; G27; G23; G26; G28;

0; 50; 3; 23; 14; 0; 0; 14; 61; 6; 27; 39; 37; 8; 46; 68; 0; 0; 0; 0;

0

s526n

G23

G14

G18

G22

G28

G13; G19 G15; G16 G12; G21 G24; G25

G11

G30

G20

G26

G10

G17

G29

G27

0; 52; 2; 23; 17;

12; 6; 20; 64 42; 62; 44; 8 35; 0; 0; 0; 0 0

7;

46;

s820

18

19

G42; G41; G39; G40; G38

0; 33; 0

s832

18

19

G42; G41; G39; G40; G38

0; 33; 0

s953

16

23

ReWhBufHS1; TgWhBufHS1; SeOutAvHS1; LdProgHS1; State_3; State_1; State_0; State_2; State_5; State_4; Mode2HS1; ReRtTSHS1; ShftIRHS1; NewTrHS1; Mode1HS1; ShftORHS1; ActRtHS1; Mode0HS1; TxHInHS1; LxHInHS1; NewLineHS1; ActBmHS1; GoBmHS1; LoadOHHS1; DumpIHS1; SeFullOHS1; GoRtHS1; LoadIHHS1; Se-FullIHS1

2;

13;

3

7

7

3

6

3

6

0

7

3

6

3

6

0

2

0

0

Flip-flops corresponding to state variables with low Po,avg(LOS) can be selected for including them in enhanced scan chains. The additional investigations are necessary for choosing the threshold values for Pa,avg.

Conclusion

The method of observability estimation based on probability calculation of robust PDF manifestation of all paths connected with a state variable in the frame of the LOS technique was developed. It allows grading state variables and including ones with low Po,avg(LOS) in enhanced scan chains.

REFERENCES

1. Xu G., Singh A. D. Achieving high transition delay fault coverage with partial DTSFF enhanced scan chains // Proc. of International Test Conference. 2QQ7. P. 1-9.

2. Gefu Xu, Adit D. Singh. Flip-flop selection to minimize TDF coverage ith partial enhanced scan // Proc. of ATS. 2QQ7. P. 335-34Q.

3. Seongmoon Wang, Wenlong Wei. Low overhead partial enhenced scan technique for compact and high fault coverage transition delay test patterns // Proc. of ETS. 2QQ8. P. 125-13Q.

4. 4Matrosova A.Yu., Melnikov A.V., Mukhamedov R.V., Ostanin S.A., Singh V. Flip-Flops selection for partial enhanced scan techniques // Вестник Томского государственного университета. Управление, вычислительная техника и информатика. 2Q12. № 2(19). C. 112-12Q.

5. Matrosova A., Andreeva A., Melnikov A., Nikolaeva E. Multiple stuck-at fault and path delay fault testable circuits // Proc. of EW&DT Symposium. Lvov. Ukraine. 2QQ8. P. 356-364.

Melnikov Alexey Vladimirovich Tomsk State University

Email: alexey.ernest@gmail.com Поступила в редакцию 28 апреля 2Q12 г.

Мельников А.В. (Томский государственный университет). Вычисление наблюдаемости триггеров в рамках LOS техники сканирования состояний схемы.

Ключевые слова: неисправность задержки пути; робастная неисправность задержки; эквивалентная нормальная форма (ЭНФ); LOS-техника сканирования состояний схемы.

Для обнаружения неисправностей задержек сигналов в схемах с памятью используется техника сканирования состояний схемы, основанная на применении специальных триггеров, функционирующих как элементы памяти в рабочем режиме и как элементы сдвигового регистра в режиме тестирования. При этом не каждая тестовая пара может поступать на входы комбинационного эквивалента схемы. Зарубежными исследователями была предложена расширенная техника сканирования, основанная на дублировании триггеров. Эта техника требует большой аппаратурной избыточности, которая не устраивает практиков. Затем была предложена частичная техника сканирования, при которой в расширенную сканируемую цепь включаются лишь некоторые триггеры. Возникает проблема их выбора. В статье приводится алгоритм оценки наблюдаемости переменной состояния, сопоставляемой триггеру, основанный на робастной тестируемости неисправностей задержек путей и ориентированный на Launch-on-Shift (LOS)-технику сканирования. Триггеры с низкими оценками наблюдаемости соответствующих переменных состояния являются претендентами для включения в расширенную сканируемую цепь. Приводятся результаты экспериментов на контрольных примерах.

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