CC BY
12
НАУЧНО-ТЕХНИЧЕСКИЙ ВЕСТНИК ИНФОРМАЦИОННЫХ ТЕХНОЛОГИЙ, МЕХАНИКИ И ОПТИКИ май-июнь 2023 Том 23 № 3 http://ntv.ifmo.ru/
I/ITMO SCIENTIFIC AND TECHNICAL JOURNAL OF INFORMATION TECHNOLOGIES, MECHANICS AND OPTICS ИНФОРМАЦИОННЫХ ТЕХНОЛОГИЙ, МЕХАНИКИ И ОПТИКИ
May-June 2023 Vol. 23 No 3 http://ntv.ifmo.ru/en/
ISSN 2226-1494 (print) ISSN 2500-0373 (online)
doi: 10.17586/2226-1494-2023-23-3-473-482
Mathematical modelling of tri-layer dielectric OTFT based on pentacene semiconductor for enhancing the electrical characteristics
Deepika Panghal1H, Rekha Yadav2
1'2 Deenbandhu Chhotu Ram University of Science and Technology, Sonepat, 131039, India
1 deepikapanghal5@gmail.comH, https://orcid.org/0000-0001-6769-0948
2 rekhayadav.ece@dcrustm.org, https://orcid.org/0000-0001-9580-9766
Abstract
Organic thin film transistors (OTFTs) are significant for several reasons because their design processes are less complicated than those of conventional silicon technology which requires complex photolithographic patterning techniques and high-temperature and high-vacuum deposition processes. The more complex procedures used in traditional Si technology can be replaced by low-temperature deposition and solution processing. OTFTs based on the single-layer dielectric medium are poor in reducing the leakage current among the source and drain channel due to the incompatible resistance of dielectric medium. The paper presents a model of a tri-layer dielectric medium based on the organic semiconductor pentacene. In this tri-layer OTFT, three different dielectric mediums are used, such as SiO2, POM-H (PolyOxyMethylene-Homopolymer) and PEI-EP (PolyEthylenelmine-Epoxy resin), for reducing the leakage current and enhancing the mobility among the source and drain channel. The parameter values, such as drain current IDS, threshold voltage Vt and mobility for the designed tri-layer dielectric OTFT, are evaluated and compared with the single layer and bi-layer OTFT models. Thus, the attained mobility, drain current and threshold voltage for the proposed OTFT model are 0.0215 cm2/(V s), -4.44 mA for -10 V gate and -2.5 V drain voltage (VDS) and threshold value 0.2445 V (Vt) for gate voltage -10 V (VG). These attained parameter values are greater than the single- and bi-layer dielectric OTFT models. Thus, the mathematical modeling of the designed tri-layer dielectric OTFT model enhances the electrical characteristics of the other OTFT models. Keywords
OTFT, SiO2, PEI-EP, POM-H, mobility, threshold voltage
For citation: Panghal D., Yadav R. Mathematical modelling of tri-layer dielectric OTFT based on pentacene semiconductor for enhancing the electrical characteristics. Scientific and Technical Journal of Information Technologies, Mechanics and Optics, 2023, vol. 23, no. 3, pp. 473-482. doi: 10.17586/2226-1494-2023-23-3-473-482
УДК 621.382.3
Математическое моделирование трехслойного диэлектрика OTFT на основе пентаценового полупроводника для улучшения электрических
характеристик
Дипика Пангал 1Н, Рекха Ядав2
Университет науки и технологий Динбандху Чхоту Рам, Сонипат, 131039, Индия
1 deepikapanghal5@gmail.coms, https://orcid.org/0000-0001-6769-0948
2 rekhayadav.ece@dcrustm.org, https://orcid.org/0000-0001-9580-9766
Аннотация
Органические тонкопленочные полевые транзисторы (Organic thin film transistors, OTFTs) широко используются по нескольким причинам. Процессы их проектирования менее сложны, чем при традиционной кремниевой технологии, которая требует особые методы фотолитографического формирования рисунка и процессов высокотемпературного и высоковакуумного осаждений. Наиболее трудоемкие процедуры, используемые в
© Panghal D., Yadav R. 2023
традиционной кремниевой технологии, могут быть заменены низкотемпературным осаждением и обработкой на твердый раствор. OTFT на основе однослойной диэлектрической среды имеют большой ток утечки между истоком и стоком из-за несовместимости сопротивлений диэлектрической среды. В работе представлена модель трехслойной диэлектрической среды на основе органического полупроводника пентацена. В трехслойном OTFT использованы три диэлектрические среды: SiO2, РОМ-Н (полиоксиметилен-гомополимер) и РЕ1-ЕР (полиэтиленимин-эпоксидная смола) для снижения тока утечки и увеличения подвижности между истоком и стоком. Выполнена оценка и сравнение значений параметров: тока стока порогового напряжения у и подвижности ^ для разработанного трехслойного диэлектрического OTFT с одно- и двухслойными моделями. Полученные значения параметров для разработанной модели OTFT при напряжении затвора Уа = -10 В составили: = -4,44 мА; ^ = 0,0215 см2/(Вс) (для напряжения стока УБ8 = -2,5 В) и У1 =0,2445 В. Полученные значения параметров оказались больше, чем в одно- и двухслойных диэлектрических моделях OTFT. Таким образом, математическое моделирование разработанной трехслойной структуры продемонстрировало улучшение электрических характеристик по сравнению с другими типами OTFT. Ключевые слова
OTFT, SiO2, РЕ1-ЕР, РОМ-Н, подвижность, пороговое напряжение
Ссылка для цитирования: Пангал Д., Ядав Р. Математическое моделирование трехслойного диэлектрика OTFT на основе пентаценового полупроводника для улучшения электрических характеристик // Научно-технический вестник информационных технологий, механики и оптики. 2023. Т. 23, № 3. С. 473-482 (на англ. яз.). doi: 10.17586/2226-1494-2023-23-3-473-482
Introduction
Organic thin film transistors (OTFTs) are currently developing an increase in attention due to the low-temperature technique and affordable manufacture. Consequently, their ability for a variety of applications is growing, including large-area flexible electronics and affordable electronic components [1]. Their useful applications include flexible screens, RF identification tags, sensors, electronic paper, etc. Furthermore, the natural flexibility of OTFT with all-polymer architectures enables the development of flexible integrated circuits [2]. Organic and polymer microelectronic device fabrication methods include thermal evaporation, printing, spin coating, and lithography [3]. A number of printing processes, such as Ink-Jet Printing (IJP), screen printing, micro contact printing, are quite interesting. The IJP approach has been receiving more attention among these printing technologies because of the polymer devices produced based on the benefits of straightforward fabrication processes, compatibility with many substrates, low temperature processing and affordability [4]. A Metal Oxide Semiconductor Field-Effect Transistor (MOSFET) and OTFT have similar operating principles.
However, the channel formation is different and operates in a voltage-controlled current source by applying a voltage between the gate and the source (VG) [5]. At this point, the charge carrier accumulation process begins at the semiconductor and insulator interface helps for the generation of current as well as the flow of current when a voltage between the drain and the source (VDS) is applied [6]. OTFT is combined using the gate dielectric and an organic semiconductor layer with electrodes that consist of source, gate and drain [7]. The arrangement of the gate dielectric can be either upward or downward that determines the structure of the OTFT. Hence, the organic semiconductor layer source and drain contacts are referred to as Top Gate (TG) and Bottom Gate (BG) based on their location and contact structures [8]. Complex integrated circuits based on OTFTs need to be characterized and modeled in advance for efficient design.
Many mathematical models of the OTFTs have been created in recent years. They mostly utilize models of conventional Metal Oxide Semiconductor (MOS) transistors that have been slightly changed by the addition of suitable experimental factors [9]. The created model need to exhibit strong efficiency in circuit simulations and sufficient accuracy in device simulations. In reality, the design must consider the material specifications and the physical foundations of the device structure. However, innovation is still in its early stages and a variety of parameters including materials and structure that can change the established model by upgrading [10]. Therefore, it's crucial to take a hands-on approach to make the model update easier. Implicit equations are included in the model because of the physical treatment with surface potential variables. Model convergence in circuit simulations will rarely be affected by this technique. Hence, The OTFT model should be derived based on the explicit equations to prevent this divergence [11]. In this paper, the parameters of the OTFT, such as capacitor factor, mobility and threshold voltage, are mathematically modeled based on the different combinations of dielectric layer, such as SiO2, PolyOxyMethylene-Homopolymer (POM-H) and PolyEthylenelmine-Epoxy resin (PEI-EP), to analyze the performance of the OTFT using F16CuPc semiconductor material. The derived parameters of the OTFT device for three different dielectric layers are used for finding the electrical characteristics. These electrical characteristics for each combinations of dielectric layer are derived and compared. As a result, the tri-layer dielectric OTFT will have better electrical properties than the existing OTFT. Major contributions of the designed model are:
— Mathematical modeling of tri-layer OTFT is derived for enhancing the electrical properties of the OTFT.
— Organic semiconductor pentacene, or F16CuPc, is used to examine the effectiveness of the developed tri-layer dielectric OTFT.
— Insulating or dielectric medium including PEI-EP, POM-H and SiO2 is used for enhancing the electrical conductivity between the source and drain.
— Parameters of the tri-layer OTFT, such as capacitor
factor, mobility and threshold voltage, are
mathematically determined.
Literature Review
Numerous techniques are introduced for enhancing the electrical conductivity between the source and drain channels which have been developed by using single-, bi-and tri-layer dielectric medium. The majority of current methods are studied and some of them are reviewed below Borthakur and Sarma [12] had designed OTFT based on top contact pentacene with bi-layer source drain electrode. The dielectric medium used in this model are N, NA'-Bis (3-methyl phenyl) — N, NA'-diphenyl benzidine with TPD/ Au bi-layer source-drain (S-D) electrodes. This bi-layer electrode shows better performance than the single-layer S-D electrode OTFT devices. The field-effect mobility, "on-off" ratio, threshold voltage and the subthreshold voltage, are attained from the designed model with TPD/ Au bi-layer source-drain electrode.
Cortes-Ordonez et al., [11] had developed an analytical and compact model of gate capacitance in OTFT. This modeling aims to validate compact capacitance of OTFTs at the accumulation from the depletion region by considering the frequency response. This OTFT is designed based on the Unified Model parameter Extraction Method (UMEM) to calculate the parameter values of the designed model. The effect associated with the density of localized states is included in the gate capacitance. Furthermore, experimental derivation of the gate capacitance and the presentation of this model forecast with a high accuracy.
Li et al., [13] had performed a mobility model based on temperature and contact resistance in organic thin-film transistors. A mobility model for OTFT is developed by taking into account contact and temperature resistance based on the device physics. The mobility model with hopping mechanism can explain that temperature and gate bias are dependent on the surface potential. It is also taken into account to determine the proper mobility when calculating the contact resistance. A DC compact model is designed for resisting the interface and temperature in the model at the range of -190 °C to 22 °C. The several comparisons among developed model and experimental data or numerical iteration provide strong evidence for the mobility and current models validity.
Cortes-Ordonez et al., [14] had performed extraction of parameter from I-V and C-V characteristics by modeling OTFTs with the temperature range of -123 °C to 77 °C. Analyses of the obtained parameters based on temperature dependency are performed. At various temperatures, an OTFT-adapted unified model and parameter extraction techniques are employed for finding the performance of the model. The experimental I-V characteristics in the linear and saturation regimes as well as the C-V characteristics at various frequencies are compared in order to validate this model.
Leise et al., [15] had developed an approach for the calculation of charges and capacitances in staggered OTFTs. The charges are produced in an analytical and concise manner using an existing DC model. To distribute
charges among the drain and source sides of the channel, a linear charge partitioning system is used. The only factors that affect the final equation are the drain and source end charge densities of the channels with geometrical features. The capacitances are compared with the results of the Centaurus Technology Computer-Aided Design (TCAD) simulation and measurement data using the compact model which is implemented in Verilog A. This model has the advantage of having a singular formulation that accounts for all operational regimes.
Numerous dielectric polymers with single-, bi-, and tri-layers are used from the above-reviewed method to improve electrical performance. In existing techniques, the mathematical modeling of single-layer dielectric medium is used for OTFT to conduct the electric current from the source to drain electrode. In those OTFT, the mobility of the charge carriers of the OTFT is poor. Therefore, the tri-layer OTFT is mathematically created to improve the electrical performance of the OTFT and the mobility of charge carriers.
Proposed Methodology
In OTFT, the flow of current among the source and drain channel is produced by an inorganic dielectric such as silicone dioxide which is employed as a dielectric polymer. Using the inorganic dielectric layers, there are advantages as well as disadvantages in the OTFT. The advantages of the inorganic dielectric are addressing the scaling issues and reducing the leakage current in the short channel OTFTs, and the disadvantages are reduction in mobility with an increase in dielectric constant and high-surface energy that reduces the mobility further. Hence, the addition of organic dielectric layers to the inorganic dielectric will enhance the mobility and reduce the leakage current in the short channels. In this mathematical model, the tri-layer dielectric medium enhances electrical conductivity of the source and drain channel. The interior structure of the tri-layer OTFT is illustrated in Fig. 1.
The variables in the tri-layer OTFT are Thickness of the semiconductor (TOX), Thickness of tri-layer dielectric medium (TOSC), Source capacitance of oxide material (COVS), Capacitive resistance for source (RC,S), Gate Resistance (RG), Gate to Source capacitance (CGS), Gate to Drain capacitance (CGD), Source to Drain Resistance (Rsd), Drain capacitance of oxide material n (COV,D) and
Fig. 1. Interior structure of the tri-layer OTFT (see below for notation definitions)
Capacitive resistance for Drain (Rcd). In this model, the «-type heavily doped silicon wafer is used as a substrate. The gate dielectric, such as SiO2, POM-H and PEI-EP, are used for controlling the flow of current at the source to drain channel. For evaluating the electric characteristics of the OTFT, an organic semiconductor such as F16CuPc and pentacene is used. Finally, the copper is used as the source and drain metal electrode. The parameters extracted from the mathematical modeling are Device threshold voltage (Vt), capacitive insulation (Cins1, Cins2 and Cins3) and Mobility (m) for three dielectric medium are evaluated.
Mathematical modeling of OTFT for extracting the parameters
In this model, the work done is based on deriving the mathematical equations for single-, bi- and tri-layer dielectric medium based OTFT model to extract the electrical parameters of the OTFT. Bottom gate-top contact is the fundamental architecture of a transistor where the length is situated among the drain and source contacts. OTFT is simply a drift mechanism like the existing Complementary Metal Oxide Semiconductor technology where the linear and subthreshold regimes are controlled by using a single equation. The derived equation for the OTFT is based on the Variable Range Hopping (VRH) model. For unipolar charge carrier (electrons) the channel conductivity from equation is defined as
g = eyn(y),
(1)
where n(y) is the electron concentration in the channel, m is the electron mobility defined as the charge velocity divided by the electric field. In the following equation, the mobility of electron is determined as
M = V/E.
Two powerful experiments are used to define the material charge mobility. The first is Time of Flight (TOF) where mobile charges are generated by photonic excitation. The charges are accelerated by external electric field (E). The mobility can be measured by the time (At), it takes the charges to move through a path of distance (L). Mobility of electrons at first TOF is determined using the following equation
L
ME
M-TOF :
Current density across the channel according to Ohm law is determined using the equation
Jx = gEx.
(2)
Substituting the equation (1) in (2) and integrating will give us the total channel current
Ix = i \Jxdydz = MEx\en(y)dy\dz.
(3)
The channel charge per unit area is defined in equation
Qch = ~\en(y)dy. (4)
y
Substituting equation (3) in (4), the following equation and determines the total channel current.
Ix = - MExÖch|dz
4 = - MExQChW,
(5)
where W is the channel width accepted by integration over
z axis and Ex = —j^. The channel charge Qch per unit area
is assumed to be constant across, and it is accumulated across the channel after flat band has achieved, which is determined at equation.
Qch = -Qns( Vg - Vx - ФШ8 - Vins(FB)),
(6)
where VG is the gate to source potential, Vx is the potential in the channel at a point x and the Cins is insulator capacitor per unit area. The insulator capacitor per unit is determined using the following equation
Eo^in
C =
where s0 and sins are the permittivity of free space and relative insulator permittivity and tins is the insulator layer thickness. Fig. 2 shows the metal, insulator and semiconductor energy levels before physical contact.
Electron affinity of insulator (ext), Electron affinity of semiconductor (exs), Insulator gap energy (Eg;), semiconductor gap energy (Egs), Fermi level for semiconductor (EFs), Fermi level for insulator (EFi), Potential difference between the intrinsic Fermi level and the doped Fermi level (eOF), Metal work function (eOm), Fermi level for metal (EFm). When metal, insulator and semiconductor materials are jointed together to form MIS capacitor, an equilibrium state occurs by Fermi level alignment between the metal work function and the semiconductor Fermi level (a short between the semiconductor bulk and the metal contact may be needed to promote this equilibrium). This equilibrium and the
LUMO
HOMO
Insulator
Fig. 2. Metal, insulator and semiconductor energy levels before physical contact
associated charging cause the HOMO and LUMO levels to bend near the interface between the semiconductor and the insulator. In addition, it causes a shift in the vacuum levels of the metal and the semiconductor. The existence of nonzero potential between the gate material and the semiconductor cause net charge to appear on both sides of the insulator. The metal-semiconductor work function difference $ms is derived from equation
E,
$ = $ - (x + -E. - $ ) ms m VAs ^
2q
where $m is the metal work function, semiconductor electron affinity, Egs is the semiconductor gap energy, q is charge, and $F is the potential difference between the intrinsic Fermi level and the doped Fermi level. In the case of non-degenerate semiconductors, it is defined by using the following equation:
Xs
is the
N
Ф^ = Vtln-
where Vt is the thermal voltage, Nd is the donor doping concentration, and ni is the intrinsic carrier concentration. The contact potential effect (the different energy levels of the metal and semiconductor) is not the only one that causes net concentration of charges. A "parasitic" charge may exist in the insulator and influence the charge concentration in the MIS device.
If the "trapped" charge is defined as Qss and if we assume it is concentrated close to the insulator semiconductor interface (as appear in Fig. 3), then the induced potential drop across the insulator is defined by using the equation.
V = ^
'ins f! ■
In this equation, the MIS capacitor is in equilibrium without external potential that can sum the energy levels using the equation
Фms ^0 Vins0-
(7)
If a gate voltage VG is applied, then the potential drop across the insulator and the surface potential changes as per the following equation
VG = A Vins0 + A9s0 = (Vins - Vins0) + ($s - $s0). (8)
Semiconductor
Semiconductor
Insulator
Insulator
Fig. 3. Flat band conditions after applying external potential
By inserting equation (7) into (8), the gate voltage Vg will be converted to the following equation
V- = V + $ + $
' G 'ins ^s ^ms-
Flat band conditions exist when no charge is present in the semiconductor and the semiconductor energy bands are flat. In this condition, the surface potential equals to zero and the charge density on the gate metal should cancel the parasitic charge existing in the insulator as defined by the following equation
Qss + Qm = 0.
Therefore, in flat band condition the gate potential is derived as equation
V^ (FB) = V + Ф =-+ Ф
' G V* ") ' ins ^ms /~< ms-
Q.
r.
^ms
Hence, the flat band condition results in the threshold voltage in the form of the following equation
ßss
V = — + Фтв = Фтв + V
ms ^ms ins(FB)-
(9)
Substituting the equation (9) in (6), we get the charge per unit as the following equation
öch = -Qns(Vg - Vx - Vt).
(10)
dVx
Substituting the equation (10) in (5) with Ex = , we
apply electric field among the drain and source contact. Then, the following equation defines the total channel current:
dVx
Ix = ^Cins(Vg - Vx - Vt)W.
(11)
Integrating (11) over the channel length L and the drain source potential VDS, the following set of equations is derived:
fb
L vd dVx
J Ix = J^—CinsV - Vx - Vt)W, 0 VS "X
L vd
JIxdx = J vWCms(VG - Vx - V)dVx,
0 vs
L vd
IxJ dx = Wins J(Vg - Vx - Vt)dVx,
0 vs
W vd Ix = Cins J(Vg - Vx - Vt)dVx.
l vs
Here, VDS = VD - VS and Ix = IDS, and then
W Vis
Idsm = Cins[Vg - Vt] Vds - —. (12)
Equation (12) can be used as long as | VDsl < I Vg - Vt|. This region is called the linear region. However, when drain-source voltage increases above this limit, section of
the channel (near the drain electrode) will move to depletion state cancelling charge accumulation at this zone. By increasing the drain-source voltage, the channel depletion zone enlarges. This bottleneck section limits the channel current by increasing the channel resistance associated with increasing the channel depletion that is affected by the drain-source voltage. In turn, this dependence causes the channel current to get into saturation region. For this case, integration of the boundaries is used, and the result looks like equation:
Leff vG-v,
J IDS(y)dy = J WCsVg - V - V)dv(y),
where Leff is the effective channel length and VG - Vt is the voltage boundaries inside Leff. For long channel transistor (L >> d in lateral transistors) the depletion section is small compared to channel length (L - Leff << L). So Leff can be written as L. Integration of the equation results in
IdsL = Wj,
V2
Wg - V]V- -
vg-v
К C
№ r Cins 1-1
[Vg - V][Vg - V] -
w
(VG-Vtf
(13)
IDS,sat = Cins [vg - vt]2-
Equation (13) can be used as long as | VDS| > | VG - Vt|. This region is defined as the saturation region.
№
W
((St)VG). Here, L and W are the length and
width of the channel, S and VG are the thickness of the semiconductor and gate voltage, respectively. In this model, three different layers of insulator are used, such as SiO2, POM-H and PEI-EP, for enhancing the conductivity of current from source to drain channel by varying the gate and rain voltage. The following two equations are an illustration of the linear drain current for tri-layer OTFT.
Id
W
DSJin = № ,
fiOËSiOî + eOePOM-H + SoePEI-EP
'Si02
'pom-h
- K.
IDS,sat = №
V2
x [Vg - V]Vds - у'
GoEsiO, eOePOM-H e0£PEI-EP
+-+-
¿sio2 ¿pom-:
ipEi-
[Vg - Vt]2
where eSiO2, ePOM-H, ePEI-EP are the relative permittivity of the insulators, such as silicone dioxide, POM-H and
is the thickness of the
PEI-EP; t
SiO2, ¿POM-H, 1 PEI-EP
insulators. The current "on-ofi" ratio is derived by dividing the maximum drain current to the minimum drain current with the same drain voltage. The description of different parameters used in the designed model for evaluating are illustrated in the Table 1 (parameters tSiO2, tPOM-H, tPEI-EP correspond to tins in Fig 2 & 3).
Model Parameter Extraction
Electrical characteristics of tri-layer OTFT, such as capacitive insulation, threshold voltage and mobility, are derived using mathematical modeling on Matlab R2020b software with the system configurations of Intel i5-3450S processor at the speed of 2.80 GHz based on 64-bit operating system and 8.0 GB Memory (RAM). In this mathematical model, three dielectric layers, such as SiO2, POM-H, PEI-EP, are used for improving the electrical conductivity of the transistor. POM-H is the perfect material for components that are meant to replace metal. It provides great stiffness and strength with low friction and high wear resistance. It has a broad operating temperature range (-40 °C to 120 °C) with good stability. Additionally, it mixes well with metals and other polymers that provide great dimensional stability in high precision moulding. Likewise, the third dielectric medium PEI-EP can possess high initial decomposition temperature up to 340 °C. By using these POM-H and PEI-EP layer, the leakage current from the channel will be reduced and this improves the mobility of the free electrons in the channel.
tp
X
0
Table 1. Description for the parameters used and derived for the tri-layer OTFT
Parameters Description Values
Lchannel Channel Length, cm 0.02
Wchannel Channel Width, cm 1
tox Thickness of the semiconductor, nm 40
Vg Gate to source Voltage, V -20 to -80
Vds Drain to source Voltage, V -2.5 to -10
s0 Permittivity of the vacuum space, F/m 8.854 10-12
sSiO2 Relative permittivity of silicone dioxide 3.9
sPOM-H Relative permittivity of POM-H 3.8
SPEI-EP Relative permittivity of PEI-EP 3.8
Thickness of the silicone dioxide insulator, ^m 0.3
tPOM-H Thickness of the POM-H insulator, ^m 0.8
tPEI-EP Thickness of the PEI-EP insulator, ^m 0.3
I-V characteristics for single-, bi- and tri-layer dielectric medium OTFT
OTFTs are tri-terminal, unipolar, voltage-controlled, high input impedance devices which are used as an integral part for vast variety of electronic circuits. The OTFT devices will be in 'off' state with a minimum current flow between source and drain electrodes when the gate voltage is not applied. If the gate voltage is applied, the electrons or holes can be induced at semiconductor/ dielectric interface that increases the source drain current ('on' state). OTFTs are mainly designed using a single dielectric medium for reducing the leakage current and enhancing the current flow at the source-drain channel. Though the single-layer dielectric medium (such as SiO2) is good in reducing leakage current, the temperature resistance is still a major drawback in the OTFT. Thus, a tri-layer OTFT mathematical model has been derived using organic dielectric medium for enhancing the temperature resistance of the device. Fig. 4 shows the I-V characteristics for single-layer dielectric medium OTFT.
Fig. 4 illustrates the I-V characteristics for three different layer OTFT models. The Vgs (V) refers to VG that represents gate to source voltage which is kept constant for drain current characteristics of MOSFET. In this mathematical model, the gate voltage has been varied
for attaining different drain current characteristics of the designed tri-layer OTFT model. I-V characteristic of the OTFT is determined by making the gate voltage (VG) constant and varying the drain voltage (VDS) to attain the drain current (IDS) of the OTFT. The single-layer OTFT consists of SiO2 as a dielectric medium, bi-layer consists of SiO2 and PEI-EP as dielectric medium and tri-layer consists of SiO2, PEI-EP and POM-H as a dielectric medium. The insulation of the substrate current will be high for the designed tri-layer OTFT due to the three insulation layer, which reduces the leakage current at the source to drain channel.
Table 2 illustrates the attained values of the drain current characteristics for the three different OTFT models. These values of the IDS (mA) are almost similar to the IDS (mA) of single- and bi-layer dielectric medium OTFT model but the resistance of the tri-layer dielectric medium has enhanced the values of the designed tri-layer OTFT than the other OTFT models.
The threshold voltage is abbreviated as Vt which is the least gate-to-source voltage (VG) required to provide a conducting route between the source and drain terminals. It is a critical scaling factor for maintaining power efficiency. In this evaluation, the threshold voltage of the three different layer OTFT model are demonstrated at Fig. 5.
-40
и
I
-80
—•— Vgs = -20 —*— Г„ = -40 -*- Vgs = -60 Vgs = -80
-10
Drain Voltage VDS, V 0
►S-40
U 1
-80
-10
Drain Voltage VDS, V
-10
Drain Voltage VDS, V
Fig. 4. I-V characteristics for single-layer (a), bi-layer (b) and tri-layer (c) dielectric media
Table 2. I-V characteristics for single-, bi- and tri-layer dielectric medium OTFT models, V
Drain voltage (VDS)
Gate voltage (VG) Single-layer Bi-layer Tri-layer
-2.5 -5 -7.5 -2.5 -5 -7.5 -2.5 -5 -7.5
-20 -3.33 -12.91 -28.75 -3.54 -13.33 -29.37 -4.44 -15.13 -32.07
-40 -3.64 -13.54 -29.69 -3.96 -14.17 -30.63 -5.76 -17.77 -36.03
-60 -3.91 -14.08 -30.50 -4.37 -15.00 -31.88 -7.08 -20.41 -40.00
-80 -4.18 -14.61 -31.29 -4.79 -15.84 -33.14 -8.40 -23.06 -43.96
Parameter Single-layer Bi-layer Tri-layer
Gate voltage (VG) -2.5 -5 -7.5 -2.5 -5 -7.5 -2.5 -5 -7.5
Threshold voltage ( Vt) -0.51 -1.03 -1.6 -0.14 -0.19 -0.25 -0.12 -0.16 -0.207
-4 0 ~'-8 -4 0-8 -4
Gate Voltage VG, V Gate Voltage VG, V Gate Voltage VG, V
Fig. 5. Threshold voltages for single-layer (a), bi-layer (b) and tri-layer (c) dielectric media of OTFT
Table 3. Threshold voltage vs. gate voltage for different layer structures of dielectric medium OTFT, V
Parameter
Single-layer
Bi-layer
Tri-layer
Gate voltage (VG)
-2.5
-5
-7.5
-2.5
-5
-7.5
-2.5
-5
-7.5
Threshold voltage (V)
-0.51
-1.03
-1.6
-0.14
-0.19
-0.25
-0.12
-0.16
-0.207
Table 3 illustrates the attained threshold voltage of three different layers OTFT for different gate voltage. Threshold voltage for minimum gate voltage is similar for three different types of OTFT but the maximum gate voltage differs a lot for the different type of OTFTs. The threshold voltage for the tri-layer dielectric medium OTFT model consist of low voltages, lower than single- and bi-layer dielectric medium OTFT model, which results in quick conduction of current among the source and drain channel.
Effective mobility of the single-, bi- and tri-layer OTFT for different pentacene thickness are illustrated at Fig. 6. The OTFT is activated by biasing the gate which begins
collecting carriers among the source and drain channels. This attraction is normal to the carrier flow that attracts channel carriers to the semiconductor-oxide interface where they can scatter off the interface. This additional scattering mechanism reduces the mobility of the carriers crossing the channel. Hence, a tri-layer dielectric OTFT has been designed to enhance the mobility of the carrier between the conduction channels.
Table 4 illustrates the effective mobility of three different layer OTFT model for different pentacene thickness. Thus, the evaluation of the effective mobility for three different layer OTFT model shows that the designed
xi 0--
Pentacene Thickness, nm
Pentacene Thickness, nm
30 50
Pentacene Thickness, nm
Fig. 6. Effective mobility for single-layer (a), bi-layer (b) and tri-layer (c) OTFT
Table 4. Effective mobility vs. pentacene thickness for different layer structures
Parameter name Single-layer Bi-layer Tri-layer
Pentacene thickness, nm 10 20 30 10 20 30 10 20 30
Effective mobility, cm2/(Vs) 0.002 0.004 0.006 0.003 0.006 0.009 0.005 0.010 0.016
tri-layer dielectric OTFT based on SiO2, POM-H and PEI-EP model performs better than the other OTFT model.
Conclusion
Mathematical modelling of tri-layer OTFT has been implemented and compared with the existing OTFT based on different layers of dielectric medium. The proposed tri-layer OTFT model designed in this research work is based on the three dielectric medium, such as SiO2, POM-H and PE-EP. For evaluating the I-V characteristics of the designed tri-layer OTFT, the pentacene semiconductor is used in this designed model. The evaluated parameters of the designed model are drain current (mA), threshold voltage ( Vt) and mobility The attained IDS (mA) from single-, bi- and tri-layer dielectric medium OTFT model for -20 V gate voltage and -2.5 V drain voltage are -3.33, -3.54 and -4.44. Then, the threshold voltage of the single-, bi- and tri-layer OTFT of 10 V (VG) are -2.072, -0.3023 and -0.2445. Likewise, the mobility of the three OTFT model for 40 nm pentacene are 0.0092, 0.0125 and 0.0215. Thus, the evaluation of the drain current (mA), mobility and threshold voltage (Vt) of three different layer dielectric medium OTFT model shows that the performance of the designed tri-layer dielectric medium OTFT model is greater than the other OTFT models. In future, the generated mathematical model will be simulated using computerised
software to evaluate the reliability of the designed model performance.
Acknowledgements
Funding
The authors declare that no funds, grants, or other support were received during the preparation of this manuscript.
Conflict of Interest
The authors declared that they have no conflicts of interest to this work. We declare that we do not have any commercial or associative interest that represents a conflict of interest in connection with the work submitted.
Availability of data and material
Not applicable.
Code availability
Not applicable.
Author contributions
The corresponding author claims the major contribution of the paper including formulation, analysis and editing. The co-author provides guidance to verify the analysis result and manuscript editing.
Compliance with ethical standards
This article is a completely original work of its authors; it has not been published before and will not be sent to other publications until the journal's editorial board decides not to accept it for publication.
References
1. Ana F., Najeeb-ud-Din. An analytical modeling approach to the electrical behavior of the bottom-contact organic thin-film transistors in presence of the trap states. Journal of Computational Electronics, 2019, vol. 18, no. 2, pp. 543-552. https://doi.org/10.1007/s10825-019-01314-6
2. Marinov O., Deen M.J., Jiménez-Tejada J.A., Chen C.H. Variablerange hopping charge transport in organic thin-film transistors. PhysicsReports, 2020, vol. 844, pp. 1-105. https://doi.org/10.1016/). physrep.2019.12.002
3. Ishaku A.A., Gleskova H. Potential of low-voltage organic transistors with high on-state drain current for temperature sensor development. Organic Electronics, 2021, vol. 93, pp. 106152. https://doi. org/10.1016/j.orgel.2021.106152
4. Jiménez Tejada J.A., Lopez-Varo P., Chaure N.B., Chambrier I., Cammidge A.N., Cook M.J., Jafari-Fini A., Ray A.K. Organic thin film transistors using a liquid crystalline palladium phthalocyanine as active layer. Journal of Applied Physics, 2018, vol. 123, no. 11, pp. 115501. https://doi.org/10.1063/L5017472
5. Krammer M., Borchert J.W., Petritz A., Karner-Petritz E., Schider G., Stadlober B., Klauk H., Zojer K. Critical evaluation of organic thin-film transistor models. Crystals, 2019, vol. 9, no. 2, pp. 85. https:// doi.org/10.3390/cryst9020085
6. Shiwaku R., Tamura M., Matsui H., Takeda Y., Murase T., Tokito S. Charge carrier distribution in low-voltage dual-gate organic thin-film transistors. Applied Sciences, 2018, vol. 8, no. 8, pp. 1341. https://doi. org/10.3390/app8081341
7. Teja K.B., Gupta N. Substrate selection framework for organic thin-film transistor based on flexibility and reliability issues. IEEE Journal
Литература
1. Ana F., Najeeb-ud-Din. An analytical modeling approach to the electrical behavior of the bottom-contact organic thin-film transistors in presence of the trap states // Journal of Computational Electronics. 2019. V 18. N 2. P. 543-552. https://doi.org/10.1007/s10825-019-01314-6
2. Marinov O., Deen M.J., Jiménez-Tejada J.A., Chen C.H. Variablerange hopping charge transport in organic thin-film transistors // Physics Reports. 2020. V. 844. P. 1-105. https://doi.org/10.1016/j. physrep.2019.12.002
3. Ishaku A.A., Gleskova H. Potential of low-voltage organic transistors with high on-state drain current for temperature sensor development // Organic Electronics. 2021. V. 93. P. 106152. https://doi. org/10.1016/j.orgel.2021.106152
4. Jiménez Tejada J.A., Lopez-Varo P., Chaure N.B., Chambrier I., Cammidge A.N., Cook M.J., Jafari-Fini A., Ray A.K. Organic thin film transistors using a liquid crystalline palladium phthalocyanine as active layer // Journal of Applied Physics. 2018. V. 123. N 11. P. 115501. https://doi.org/10.1063/L5017472
5. Krammer M., Borchert J.W., Petritz A., Karner-Petritz E., Schider G., Stadlober B., Klauk H., Zojer K. Critical evaluation of organic thin-film transistor models // Crystals. 2019. V. 9. N 2. P. 85. https://doi. org/10.3390/cryst9020085
6. Shiwaku R., Tamura M., Matsui H., Takeda Y., Murase T., Tokito S. Charge carrier distribution in low-voltage dual-gate organic thin-film transistors // Applied Sciences. 2018. V. 8. N 8. P. 1341. https://doi. org/10.3390/app8081341
7. Teja K.B., Gupta N. Substrate selection framework for organic thin-film transistor based on flexibility and reliability issues // IEEE
on Flexible Electronics, 2022, vol. 1, no. 2, pp. 141-149. https://doi. org/10.1109/jflex.2022.3178674
8. Dadhich S., Dwivedi A.D., Mathur G. Numerical simulation and analytical modelling of C8-BTBT-C8 organic transistor and analysis of semiconductor thickness. Lecture Notes in Electrical Engineering, 2022, vol. 862, pp. 669-680. https://doi.org/10.1007/978-981-19-0252-9_60
9. Jo S.W., Cho S., Kim C.H. Key factors affecting contact resistance in coplanar organic thin-film transistors. Journal of Physics D: Applied Physics, 2022, vol. 55, no. 40, pp. 405101. https://doi. org/10.1088/1361-6463/ac8124
10. Pruefer J., Leise J., Borchert J.W., Klauk H., Darbandy G., Nikolaou A., Iniguez B., Gneiting T., Kloes A. Modeling the short-channel effects in coplanar organic thin-film transistors. IEEE Transactions on Electron Devices, 2022, vol. 69, no. 3, pp. 10991106. https://doi.org/10.1109/ted.2022.3145779
11. Cortes-Ordonez H., Jacob S., Mohamed F., Ghibaudo G., Iniguez B. Analysis and compact modeling of gate capacitance in organic thin-film transistors. IEEE Transactions on Electron Devices, 2019, vol. 66, no. 5, pp. 2370-2374. https://doi.org/10.1109/ ted.2019.2906827
12. Borthakur T., Sarma R. Top-contact pentacene-based organic thin film transistor (OTFT) with N,N'-Bis (3-methyl phenyl)-N,N'-diphenyl benzidine (TPD)/Au bilayer source-drain electrode. Journal of Electronic Materials, 2018, vol. 47, no. 1, pp. 627-632. https://doi. org/10.1007/s11664-017-5820-2
13. Li N., Deng W., Wu W., Luo Z., Huang J. A mobility model considering temperature and contact resistance in organic thin-film transistors. IEEE Journal of the Electron Devices Society, 2020, vol. 8, pp. 189-194. https://doi.org/10.1109/jeds.2020.2974031
14. Cortes-Ordonez H., Haddad C., Mescot X., Romanjek K., Ghibaudo G., Estrada M., Cerdeira A., Iniguez B. Parameter Extraction and Compact Modeling of OTFTs From 150 K to 350 K. IEEE Transactions on Electron Devices, 2020, vol. 67, no. 12, pp. 5685-5692. https://doi.org/10.1109/ted.2020.3032082
15. Leise J., Pruefer J., Darbandy G., Seifaei M., Manoli Y., Klauk H., Zschieschang U., Iniguez B., Kloes A. Charge-based compact modeling of capacitances in staggered multi-finger OTFTs. IEEE Journal of the Electron Devices Society, 2020, vol. 8, pp. 396-406. https://doi.org/10.1109/jeds.2020.2978400
Journal on Flexible Electronics. 2022. V. 1. N 2. P. 141-149. https:// doi.org/10.1109/jflex.2022.3178674
8. Dadhich S., Dwivedi A.D., Mathur G. Numerical simulation and analytical modelling of C8-BTBT-C8 organic transistor and analysis of semiconductor thickness // Lecture Notes in Electrical Engineering. 2022. V. 862. P. 669-680. https://doi.org/10.1007/978-981-19-0252-9_60
9. Jo S.W., Cho S., Kim C.H. Key factors affecting contact resistance in coplanar organic thin-film transistors // Journal of Physics D: Applied Physics. 2022. V 55. N 40. P. 405101. https://doi.org/10.1088/1361-6463/ac8124
10. Pruefer J., Leise J., Borchert J.W., Klauk H., Darbandy G., Nikolaou A., Iniguez B., Gneiting T., Kloes A. Modeling the short-channel effects in coplanar organic thin-film transistors // IEEE Transactions on Electron Devices. 2022. V. 69. N 3. P. 1099-1106. https://doi.org/10.1109/ted.2022.3145779
11. Cortes-Ordonez H., Jacob S., Mohamed F., Ghibaudo G., Iniguez B. Analysis and compact modeling of gate capacitance in organic thin-film transistors // IEEE Transactions on Electron Devices. 2019. V. 66. N 5. P. 2370-2374. https://doi.org/10.1109/ted.2019.2906827
12. Borthakur T., Sarma R. Top-contact pentacene-based organic thin film transistor (OTFT) with N,N'-Bis (3-methyl phenyl)-N,N'-diphenyl benzidine (TPD)/Au bilayer source-drain electrode // Journal of Electronic Materials. 2018. V. 47. N 1. P. 627-632. https://doi. org/10.1007/s11664-017-5820-2
13. Li N., Deng W., Wu W., Luo Z., Huang J. A mobility model considering temperature and contact resistance in organic thin-film transistors // IEEE Journal of the Electron Devices Society. 2020. V. 8. P. 189-194. https://doi.org/10.1109/jeds.2020.2974031
14. Cortes-Ordonez H., Haddad C., Mescot X., Romanjek K., Ghibaudo G., Estrada M., Cerdeira A., Iniguez B. Parameter Extraction and Compact Modeling of OTFTs From 150 K to 350 K // IEEE Transactions on Electron Devices. 2020. V. 67. N 12. P. 56855692. https://doi.org/10.1109/ted.2020.3032082
15. Leise J., Pruefer J., Darbandy G., Seifaei M., Manoli Y., Klauk H., Zschieschang U., Iniguez B., Kloes A. Charge-based compact modeling of capacitances in staggered multi-finger OTFTs // IEEE Journal of the Electron Devices Society. 2020. V. 8. P. 396-406. https://doi.org/10.1109/jeds.2020.2978400
Authors
Deepika Panghal — Research Scholar, Department of ECE, Deenbandhu Chhotu Ram University of Science and Technology, Sonepat, 131039, India, https://orcid.org/0000-0001-6769-0948, deepikapanghal5@gmail. com
Rekha Yadav — D.Sc. Associate Professor, Department of ECE, Deenbandhu Chhotu Ram University of Science and Technology, Sonepat, 131039, India, sc 57208815836, https://orcid.org/0000-0001-9580-9766, Rekhayadav.ece@dcrustm.org
Авторы
Пангал Дипика — магистр, исследователь, Университет науки и технологий Динбандху Чхоту Рам, Сонипат, 131039, Индия, https:// orcid.org/0000-0001-6769-0948, deepikapanghal5@gmail.com
Ядав Рекха — доктор наук, доцент, Университет науки и технологий Динбандху Чхоту Рам, Сонипат, 131039, Индия, sc 57208815836, https://orcid.org/0000-0001-9580-9766, Rekhayadav.ece@dcrustm.org
Received 21.01.2023
Approved after reviewing 22.03.2023
Accepted 16.05.2023
Статья поступила в редакцию 21.01.2023 Одобрена после рецензирования 22.03.2023 Принята к печати 16.05.2023
Работа доступна по лицензии Creative Commons «Attribution-NonCommercial»
