CC BY
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LOGIC NETWORKS APPLICATION FOR COMPUTING PROCESS ORGANIZATION
BONDARENKO M.F., HAHANOVA I. V.__________________
Kharkov National University of Radio Electronics, Lenin ave, 14, Kharkov, 61166, Ukraine. Tel.: +380-572-702.1326. E-mail: [email protected]
Abstract. Component categorical models for analysis and synthesis of phrases and semantic structures of Russian language are offered. The models are used for dedicated microprocessor design. Such microprocessors can simulate the functions ofhuman intelligence on the basis of parallel and pipeline calculus. An example of synthesis and implementation of a model for analysis of adjectives is given. Comparison characteristics ofdesigned systems-on-chip for different types ofprogrammable logic integrated circuits are presented as well.
Introduction. Nowadays the production, which is supplied to the electronic technologies market, is used in all spheres of human activity. Such companies as Intel, Motorola, Advanced Micro Devices, IBM, SunMicrosystems and Hewlett-Packard spend millions of dollars on development of powerful microprocessors, which operate with 64 and 128-bit data. The transistors areal density on chips is 200 millions per square centimetre [1]. Microminiaturization, speed-up, decrease in value of microprocessors are the most important for electronic technologies market. It is concerned with the fact that the number of microprocessors used by people in their offices, houses and cars has increased. According to information of firm Motorola this number will run up to 400 during the next 4 years. Thus, it is actual to introduce new technologies of creation of microminiature dedicated microprocessors, which works in real time. Such microprocessors should solve the tasks of artificial intelligence with the means, close to thought processes. The successful solution of mentioned problem can be found reasons, described in the next two paragraphs.
l.The development of electronic technologies market
The increase in efficiency of medium and small microprocessors canbe noticed on the electronic technologies market. It is obvious that market opportunities will exceed the demand within the next five years. Therefore, the corporations, which produce only powerful general-purpose microprocessors can lose their profit. To avoid this they reorganize the part of the production to produce customized chips and systems-on-chip. The yearly sales of market of microprocessors are $ 40 billions.
The yearly sales of market of microprocessors are 40 billions of dollars. The market has 4 levels of hierarchy. The top level include powerful microprocessors, which are used in servers and workstations. On the second level there are personal computers. The processors of firm Intel dominate on this level. According to information of Semiconductor Industry Association (San Jose) the yearly sales of this chips in USA came to 32 billions of $ in 2000 and $23 billions in 2001. The third level is presented by microcontrollers. They gave a profit of $ 10 billions in 2001. The last level consists of digital signal-processors, which are used in cellular phones and DVD-players. The yearly sales of them were $4 billions in 2001.
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The powerful microprocessors are used for 3D games, speech-to-text translators, digital video-files editing. In the near future this tasks will be solved by special-purpose microprocessors. For the majority of users the computer is a mean for text editing and access to Internet and E-mail. Therefore the use of powerful microprocessors Itanium and Pentium (Intel), Athlon (Advanced Micro Devices), which realize a billion operations per second, for this purposes is redundant. Onthe other hand, reliability is the main competitive ability index. The second by value is customization, offered by Dell company. When the market opportunities exceed the demand, the attention is focused not on the speed-up but on improvement of characteristics for which the user is ready to pay extra money. Such characteristics are reliability, comfort, customization.
Really, the developers of microprocessors offer the characteristics, which exceed user’s needs. For example, the developers of microprocessors produce more transistors on chip than it is necessary for designers. As early as 1996 the company National T echnology Roadmap for Semoconductor paid attention on the fact that production of transistors increase annually on 60% while the use of transistors in new proj ects increase only on 20%. For this reasonthe re-orientation of means on realization of necessary and customized characteristics only is taking place in the field of microelectronics.
The modularity of devices is being developed. Such approach has been already realized on the lower levels of microprocessors design as system-on-chip. Such system consists of IP modules, which can be reused. The IP modules have different size and functions. The companies (Tensilica, ARC Cores, Hewlett-Packard u STMicroelectronics) propose to select components and characteristics right in microprocessors. It is allowed to determine the number of commands and operations, which are processed simultaneously, and to combine Digital Signal Processing with other functions on the same chip for Hewlett-Packard HP/ST Lx family.
Thus, the development of special-purpose systems-on-chip should be based on: 1) Modularity of projects. The projects should consist of reused and reconfigurable IP modules. 2) Possibility of realization of system on single chip. 3) Time decrease of design and application of customized processors and SoC. Broad opportunities for digital systems design and verification, which essentially reduce the time needed for creation of complete product.
2. The mathematical tools of categories theory
The mathematical tool of categories is oriented on problem of development of effective firmware systems-on-chip. The main components of them are functional relations between sets, which are presented by graph nodes.
The theory of categories [2,3,4] is a formal description language of internal structure of mathematical objects. It study the structure of different mathematical concepts, the relations between objects structure and their properties. The theory of categories is an important part of theoretical footing of artificial intelligence study.
The intelligence should be considered to be the realization of part of theory of categories. Single thoughts are the objects of categories. Mentation is a morphism, the architecture of
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mentation is a concrete category, described by commutative diagram. The steps in intelligence evolution are functors. The elements of theory of categories are given below.
Let M to be some set. Its elements f, g, h are called morphisms.
Let fg some partial operation, multiplication of morphisms f and g.. The operation acts from M x M to M. Sign x - is a Cartesian product of sets.
The morphism e e M is called unit or identity morphism if there is a product ee and fe=f and eg=g for any f, g e M, for which a products fe, ege M exist.
The unit morphisms e and e' are called right for morphism f and left for morphism g, iffe=f and e'g=g. It is exists only one right and only one left unit morphism for any morphism.
The product fg exists if and only if right and left unit morphisms for f and g coincide.
The multiplication of morphisms is associative (fg)h=f(gh) for any f, g, h e M, for whichthe products (fg)h and f(gh) exist.
A set of morphisms with unit morphisms, which satisfy conditions, listed above, is called object-free category K.
M=MorK is a set of all morphisms from category K.
f e MorK - morphism f is a K-morphism.
The set of all objects of category K can be written as O to K.
Obj ects are named by letters A, B, C. A e O to K - A is a K-
object; f: A ^ B or A__L__^ B - fis a morphism from object
A to B. Obj ect A is a beginning of morphism f, B -is the end of morphism f.
Each pair (A, B) of objects A, B e O to K is associated with some empty set HK(A, B) ). Such set can be also written as HomK(A, B), MorK(A, B), K(A, B), H(A, B), Hom(A, B), Mor(A, B).
There is one and only one pair of objects A and B such as
A, B e O to K and f e HK(A, B) for each morphism f e MorK.
The category with objects K consist of set of objects O to K. This two sets don’t overlap.
The category K is characterized by properties:
1) Each pair (A, B) of objects A, B is associated with set of morphisms HK(A, B) This set is included in MorK.
2) There is one and only one pair of objects A, Be O to K, such as f e HK(A, B) for each morphism f e MorK .
A=domf (dom - domain), B=codf (cod - co-domain).
3) The partial two-place operation - the multiplication of morphisms is determined in set MorK.
The product fg of morphisms f: A ^ B and g: C ^ D is determined if and only if B=C. In this case the product fg is a morphism from obj ect A to obj ect D. It is said that mapping Hk(A, B) x Hk(B, C) ^ Hk(A, C)is determined for objects A,
B, Ce K. Morphisms f, g of form f: A ^ B and g: B ^ C ( f: A ^ B and g: A ^ B) are called sequential (concurrent ).
4) The multiplication of morphisms is associative:
(fg)h=f(gh) (1)
if morphisms (fg)h and f(gh) exist. Diagram, composed of objects and morphisms of some category is called commutative diagram if the product of morphisms along any path depends on the beginning and the end of the path only.
5) It exists a morphism eB: B ^ Bcalled unit or identity morphism for each object Be O to K.This morphism is such that This morphism is such that
f. eB=f u eB * g=g (2)
for any morphisms f: A ^ B u g: B ^ C. Expressions (2) are called categorical laws of identity. They can be illustrated by following commutative diagram.
The product fg exist if and only iff, g are sequential morphisms of category K.
Category 1. There is only one object in set O to(1) and only one arrow in set Mor(1). In other words, domf=codf=a, as there is only one object a.
1a=f is an identity morphism as f -is the only morphism.
The product of morphisms should be determined for only one pair(f, f), assuming ff=f.As 1a. f=f. 1a=ff=fand f(ff}=(fE)f=fwe have the identity.
Anything can be as object a and morphism f. For example, a can be a set with identity function f .
Category 2. There are two objects 0, 1 and three arrows
(0, 0), (0, 1) u (1, 1).
(0, 0) (1, t)
Q <o’i> >9
Let: (0, 0): 0 ^ 0; (0, 1): 0 ^ 1; (1, 1): 1 ^ 1.
Then: (0,0)=10; (1,1)=1a.
The universe U is set. Optional subsets of U stand as objects A, B, C of category Pred. The system of all subsets of U stands as set O to Pred.
Predicate interpretation of morphisms.Any linear logical operator Ff(P)=Q is used as morphism f A ^ B of category Pred. This operator converts predicate P to Q:
3 xe A(Kf(x, y). P(x))=Q(y) (3)
P(x)is defined on set A, Q(y) is defined on set B. Predicate P(x)on A is an instance of object A, Q(y) on B is an instance of object B. Predicate Kf(x, y)is a kernel of linear logical operator. It fully describes conversion (3).
Kfx, y) is set on A x B. . Morphismfofform (3) is fully defined by predicate Kf(x, y). The system of operations of form (3) is a set Mor(A, B).
For each morphism f e Pred of category Pred there is a kernel Kf(x, y) of conversion (3). Each morphismf: A ^ B of category
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Pred can be defined by corresponding predicate Kfx, y) on A x B. The set Mor Pred can be found by union of MorPred(A, B) where (A,B) are various pairs of sets A, B c U. It canbe also found by set of conversions (3) with kernels K(x, y) defined on Cartesian products A x B.
Morphism f: A ^B is operation (3) FfP)=Q, g: B ^ C is operation Fg(Q)=R:
3 ye B(Kg(y, z). Q(y))=R(z) (4)
Variable predicate R(z) is defined on set C.Fixed predicate Kg(y, z) is defined on B x C. Operation Fh(P)=R canbe formed by superposition of FfP)=Q and Fg(Q)=R:
Fh(P)= Fg(Ff(P))=R.
The expression for conversion of Fg is obtained by substitution of (3) into (4):
3 ye B(Kg(y, z). (3 xe A(f y)P(x))))=R(z),
This expression convert predicate P(x) on A into R(z) on C. The latter equality will be the following after identity substitutions:
3 xe A(( 3 ye B(f y). Kg(y, z)))P(x))=R(z) (5) Equality (5) is a linear logical operator. The predicate
Kh(x, z)= 3 ye B(Kfx, y). Kg(y, z)) (6)
on A x C with arguments x e A u z e C stands as a kernel of operator.This predicate is assigned with symbol Kh(x, z).Then, equality (5) will be the following:
3 xe A(Kh(x, z) P(x))=R(z) (7)
Conversion (7) is a morphism h: A ^ C of category Pred and it can be considered as a result of multiplication of morphisms f and g: fg=h.
Identical morphisms in category Pred.
The equality predicate DA(x, y) on A x A:
eA(x, y)=DA(x, y)= V xaya.
asA
stands as a kernel of morphism eA: A ^ A of category Pred. The concept of category modified in such a way is called modified. Modified object-free category K is defined as algebra onMorK. The elements of MorK are called morphisms. The operation of multiplication of morphisms f and g stands as a basic operation of modified object-free category K. This operation acts from MorK x MorK to MorK. It is associative: :(fg)h=f(gh) for any f, g, he MorK.
The identity morphism stand as a basic morphisms in modified object-free category K. The identity morphism e (e') is called left (right) identity morphism if it meet the condition ef=f (fe'=f).
5) For each object B e O to K there is only one morphism eB: B ^B called identity morphism,such as:
a) eB . eB=eB for any eB: B ^ B;
6) f. eB=f and
B)eB . g=g for any morphisms f: A ^ B g: B ^ C.
Duality principle reads as follows: for each category K exists dual to it category K*. The last one is built by source category K with using of dual predicates: let Z -predicate about
category K, Z * - predicate about category K*; predicate Z *
is dual to Z, if it is obtained fromZ by substitution of all entering of names K of source category with name K* of dual category; substitution of all dom records with cod and vice-versa - cod with dom; substitution of names f, g, h of morphism of category K with names f*, g*, h* of dual morphism of category K*, also substitution of morphism product f. g of category K with dual morphism product g* o f* of category K*. For true predicate e about category K corresponds dual to it 2 * about category K*.
Let h=f. g is true. Then, passing to dual predicate, we can obtain h*=g* o f*. Thus: (f• g)*=g* o f*.
Associative property (fg)h=f(gh), which is predicate about category K, corresponds dual predicate h* o (g*Gf*)=(h* o g*) o f* about category K*. The next diagram responds to this property, dual to the mentioned earlier:
Properties, dual to identical mophism a) eB. eB=eB o eB* o eB*=eB*; 6) f. eB=f O eB* ° f*=f*; b) eB• g=g •O g* o eB*=g* For any morphisms f*: A^B and g*: C ^ B of category K*.
Due to the duality principle, we can define morphism f* of category Pred*, dual to f of category Pred. £ *predicate is built dual to £ . As £ we get equation (3), which defines view of morphism f. Performs substitution offwith f*, A with B, -changing of beginning and ending of morphism f; variables x and y, due to submission to sets A and B (x e A, ye B); predicates P(x) and A and Q(y) with B. In result we get predicate £ , or definition of morphism f*:
3 ye B(Kf*(y, x). Q(y))=P'(x). (8)
Core Kf(x,y) defines connection between variables x and y for morphism f, and core Kf*(y,x) - relation between the same variables for morphism f*. This connection must remains the same. It means, that predicates Kf(x,y) and Kf*(y,x) mustbe the same: Kf*(y,x)xy =Kf*(x,y).
Final definition for morphism f* is
3 ye B(Kf(x, y). Q(y))=P'(x) (9)
At the figure connectionbetween morphisms f, g, h represented by left diagram; rotation of arcs in diagram makes dual diagram (right diagram):
or equation dual to (9), substitute in (9) Kf(x,y) with A x B predicate Kf*(y,x) with B x A; Kg(y, z) with C x D predicate Kg*(z,y) with D x C; Kh(x, z) with A x D predicate Kh*(z,x) with D x A. Moreover, in expression 3ye B n C and C, Kf* and Kg* are swapped. Finally:
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Kh*(z, x)= 3ye B n C(Kg*(z, y) Afy,x)) (10)
Represented category algebra regulate main rules of functional relation models creation and modification, using in parallel computation, connected to thought process in synthesis and analysis of Russian language structures. As practical implementation of computer demonstrative example, implemented to programmable logical integrated circuit should be considered logical net analysis process model, which describes Russian language adjective declension.
is reached. Stability criterion is reaching identical state for all nodes in two adjacent steps (differences are absent in two adjacent steps).
Device interface is developed for implementation to chip and observation of operation in purpose of verification (fig.2). Bidirectional buses are used for reading from nodes and for data transfer to nodes. Signal “Ready” = 1 means successful termination of analysis operation. One or more node has empty set value if signal “Empty” = 1.
3. Logic network analysis process implementation
For implementationproposed net model (fig. 1) which executes Russian language adjective analysis. Net allows defining other properties of word based on defined properties. VHDL language [5,6] is used for formal description of specification and design development.
y2 - gender\
y: - number \ ux - stressed y - type of ending
y3 - case \ u2 - palatalization xx- first letter of ending
t - archaism \ u4 - last letter of xz- second letter of ending
y4 - animate stem x3- third letter of ending
v - sells of paradigmN, u - stem type x - ending
Clk
reset
Ready v(max_v:0) y4(max_y4:0] empty y(max_y:0) y1(max_y1:0) y2(max_y2:0) y3(max_y3:0) t(max_t:0) u(max_u:0) u1(max_u1:0] u2(max_u2:0; u4(max_u4:0' x(max_x:0) x1 (max_x1:0] x2(maxx2:0' x3(max_x3:0]
Inputs: Clk, Reset, Set
Outputs :Ready, Empty Bidirectional buses : v(max_v-l:0); y(max_y-l : 0); yl(max_yl-l : 0); y2(max_y2-l : 0); y3(max_y3-l : 0); y4(max_y4-l : 0); t(max_t-l : 0);
u(max_u-l : 0); ul(max_ul-l : 0) u2(max_u2-l : 0) u4(max_u4-l : 0) x(max_x-l : 0); xl(max_xl-l : 0); x2(max_x2-l : 0); x3(max_x3-l : 0));
net
Fig. 1. Logical net of functional relations
Model represented as net: nodes are sets of word attribute values, arcs are relations between they. Initially each node contains complete set of attributes, typical for it. Iterative process ofparallel data transfer to adjacent nodes is executing
Fig .2 Device interface
Inputs “clk”, “reset” and “set” are used for synchronization, reset and control of data putting in logical net analysis device process.
Fig. 3 represents structure of Russian language adjective analysis device. Sequential elements marked by square shapes. They hold current sets of attributes. Rectangles are
u2 out
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Fig.3. Structure of analysis device
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combinational parts, decoders, which implement functional relations between sets. Note, “dec_inv” is relation reversed to respective “dec”.
Let M={ai, a2, ... , ak} - fixed set ofK elements, A - any subset of this set, A ^ M. Attribute of set A will be binary vector (aj,a2,...,ak ) length is K (number of elements in set M). If ai=1, then ai£ A; else if ai =0, then ai^ A. Functional relations are coded with using of binary matrix, which represented in model as one-dimension vector due to features ofVHDL syntax, fig. 4.
u-u1, 7x2 BeiXHH KyobM CHHHH cegoft cnaObM cyxoft pbEKHH
5 1 i 1 0 1 0 1
y 0 0 0 1 0 1 0
Fig.4. Vector of ajuctive codes
Since all nodes have only one input, AND gates are introduced to the structure. They execute intersection of input sets.
Fig.5 outlines description of elements interface which are corresponding to nodes of the net and decoders. Inputs “Clk”, “Reset” and “Set” are control. Input “S_set(N-1:0)” is used for initial data entry, in presence of signal “set” = 1. “S_in(N-1:0)” - input is used in device work cycle. Outputs “Ready” - process done, “Empty” - node holds an empty set, “S_out(N-1:0)” - set of the nodes.
Inputs:
Clk - clock Reset Set-
S_set(N-l:0) - input set vector S in(N-l:0) - internal input set vector Outputs:
Ready
Empty - node holds empty set S_out(N-l:0) - output set vector
entity dec is
generic(nl: natural :=max_u; n2: natural:=max_ul; ratio: std_logic_vector:=ratiol); port(input: in std_logic_vector(nl-l downto 0); output: out std_logic_vector(n2-l downto 0)); end entity;
entity dec_inv is generic(nl: natural :=max_u; n2: natural:=max_ul; ratio: std_logic_vector:=ratiol); port(input: in std_logic_vector(n2-l downto 0); output: out std_logic_vector(nl-l downto 0)); end entity;
Fig.5. Elements interface description
Modern design process of digital devices using programmable logic devices (FPGA, CPLD) contains the next stages: design entry, automated synthesis, implementation and programming oftarget chip [7,8]. Simulation and verification are performed on each stage in purpose of assurance in adequacy of design to requirement specification and to appreciate its timing parameters. At stage of design, synthesis and implementation for testing VHDL models are used, with corresponding levels and detailing degree of design description. In this case it’s suitable to use tests represented as test bench [9] or in form of scripts. Testing is performed in Acive-HDL and ModelSim design verification systems. For calculation of timing parameters of real device library primitives are used, supported VITAL standard.
Code fragments, represented below, contain component types description, entering in structure of functional synthesizable VHDL model.
Listing.
--Set definition package,
-- attributes and functional relation library IEEE;
use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; package parametrs_net is -- constants - max size of set
constant max_u1: natural:=2; --{6, y}
-----Relations type -----
— Type ratio of std_logic_vector;
—u-u1, 7x2
constant ratio1: std_logic_vector (max_u*max_u1-1 downto 0) : =
"11101010001010";
--y-x1, 13x8
constant ratio2: std_logic_vector (max_y*max_x1-1 downto 0) : = "1000000000000000000001111101111110000000111111000000 0000000100000000000001111100000001000001000000000000"; -- 1000000000000 --a -- 0000000011111 --u -- 0111111000000 --e -- 0111111000000 — o -- 0000000100000 --y
-- 0000000011111 —bi
— 0000000100000 --to
-- 1000000000000 --H
end parametrs_net; library IEEE;
use IEEE.STD_LOGIC_1164.all; use IEEE.std_logic_unsigned.all; use work.parametrs_net.all;
--------DEVICE MODEL-----------
library IEEE;
use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; use work.parametrs_net.all; entity net is
port(Clk, reset, set: in STD_LOGIC;
Ready: out STD_LOGIC; empty: out STD_LOGIC;
--input s-outputs
v: inout STD_LOGIC_VECTOR (max_v-1 downto 0) ;
...);
end net;
architecture net of net is
---- components declararions ------
component node
generic (N: positive:=2); port (
S_in: in std_logic_vector(N-1 downto 0); S_set: in std_logic_vector(N-1 downto 0) ; clk, enable, reset, set: in std_logic;
S_out: out std_logic_vector(N-1 downto 0) ; ready: out std_logic; empty: out std_logic) ; end component; component dec is
generic (n1: natural:=max_u; n2: natural:=max_u1; ratio: std_logic_vector:=ratio1) ; port (
input: in std_logic_vector(n1-1 downto 0); output: out std_logic_vector(n2-1 downto 0) );
■ S_in(N-1:0) S_out(N-1:0)
■ S_set(N-1:0) empty
* clk ready
- enable
node
input(n1 -1:0) output(n2-1:0)
dec
input(n2-1:0) output(n1-1:0]
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end component; component dec_inv is
generic (n1: natural:=max_u; n2: natural:=max_u1; ratio: std_logic_vector:=ratio1) ; port (
input: in std_logic_vector(n2-1 downto 0); output: out std_logic_vector (n1-1 downto 0)); end component;
begin
-- components instantiations --Unit_V: node
generic map(N => max_v) port map( S_in => v_in,
S_set => v_set, clk => clk, enable => enable, reset => reset, set => set,
S_out => v_out, ready => ready_v, empty => empty_v ) ;
--Decoders --—u-u1, 7x2 U_u_u1: dec
generic map (n1 => max_u, n2 => max_u1, ratio => ratio1)
port map(input => u_out, output => u_u1); U_u1_u: dec_inv
generic map (n1 => max_u, n2 => max_u1, ratio => ratio1)
port map(input => u1_out, output => u1_u); end net;
Synplify Pro (Synplicity) [10] is used for synthesis [11,12,13] - transformation offunctional model to gate level circuit. ISE WebPack (Xilinx) is used for implementation. Target chip is XilinxFPGA [ 14]: XCV300E. Fig.6 represents topology of chip with placed design. This view presented by FloorPlaner tool from ISE Webpack package. Figure show that used modules are grouped together. This fact allows using short interconnections, which have fewer delays. This allows to device speed increase. FloorPlaner tool allows manual placing of modules in topology.
T iming diagrams of input and output signals (Fig.7) are built based ontiming parameters report, obtained in implementation process.
Fig. 6. Design placing topology
Fig. 7. Timing diagrams of design verification
For suitable analysis of device algorithm process, interface C++ program was developed (fig.8). Due to the PLI (Programming Language Interface) library data can be transferred to and from the model in simulation process. Additional top-level module is used for interfacing of C++ program and VHDL model. This module is developed using Verilog HDL, because PLI library developed for Verilog language [15].
[x : ' frlfft/. ». 01. «. HI). «. W.Ofp. (H) . «A. (M.tMj. I». Wl. fed. . t*U. fed. 06. H
\f /a.tfe.ne. c*. «i. jia.ue. m. t*i.i.**. t*
[77 i. i. 3. *. V 6. ?. 9. *.i0.n.iM3.w.i$.i«.iM&.i*.SO.*i.ia.».Ji.»
,L 4.C [7 n.M. | u WTMS. KLIlbA. . COKd. CMSti . ClWlMl . tJKM
ii «.o .M.a .y.M.d .a. | jj: | ill:
112: r .*. n.M. K.iQ.i | :J. s ,a,*,,t. | u2. *0.
|x$' H.Ch.y.-. v*' n.i. u4' ti .n .f .i.r.*. S.r, ..P.n.n.fl .p. f .a.t’-*.«-').w.ui.
Fig. 8. Interface programm window
4. Conclusion
1. Described mathematical apparatus is used for creation of functional relations of Russian language adj ective declension model.
2. Complete functional relations mathematical model for Russian language adjective declension is created in form of logical net.
3. Testing and verification structure is implemented based on creation ofinterface between C++ and Active-HDL simulation program.
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155
Verilog TestBench
VHDL model of design
I
Verilog compilator
I
Simulation
Internal design representation
Access
internal
structures
PLI Library Routines
£> ,n C program
»— Vi £ <D to input data
_Q and to output
— O simulation
result
Fig. 9. Top-level interfacing module
4. Device implementation in Xilinx FPGA chip: design entry, testing (Active-HDL 5.2), synthesis (Synplify 7.0), implementation (ISE WebPack 5.1), post implementation testing (ModelSim XE 5.6). Comparative analysis was performed for features of device, implemented in different chips (Fig. 10). Performance/cost relation is shownfor different types of chip (fig. 11).chips (fig. 10). Performance/cost relation is shown for different types of chip (fig. 11).
Chips Gates Parts, % I/O, % Clk, ns Freq, Mhz
xc2s200fg256-5 5546 18 76 20,781 48
xc2s200fg456-6 5546 18 47 18,505 54
xc2s200fg256-6 5546 18 76 17,29 57,8
xc2s200pg208-6 5546 18 95 18,35 54,4
xc2s150fg256-6 5546 24 76 18,619 53,7
xc2s100fg256-6 5546 35 76 18,14 55
xc2s50fg256-6 5546 56 76 18,645 53,6
xc2s30fg256-6 101
xc2s50eft256-6 5546 56 75 22,04 45
xc2s50eft256-7 5546 56 75 19,692 50,7
xc2s100eft256-6 5546 35 75 21,116 47,3
xc2v40fg256-6 117
xc2v80fg256-6 84 112
xc2v250fg256-6 5549 28 78 10,712 93
xcvp2fg256-6 5549 30 96 9,777 102
xcv50efg256-6 5546 56 76 19,972 50
Fig. 10. Different implementation features
♦ Frequency, MHz M Cost, $
60,00 -
♦—* * ^
/ //
Fig. 11. "Processing speed - cost" relation analysis
Synchrosignal period of clock and used chip space relation represented at Fig. 12.
Fig. 12. "Processing speed - space" relation analysis
5. Obtained features of digital device, implemented to chip, provide speed increase in 90-120 times, comparing to C++ implementation. At the same time, full design cycle, including testing and verification, is two weeks.
6. Further design of hardware tools for syntax and semantic analysis of Russian language with using of offered design template and functional models is just question of time.
7. Offered design is a component of “Speech-to-text” device, entering in the part of specialized processor for effective salvation of Artificial Intelligence tasks based on using of category apparatus.
References: 1. Bass M.J. and Cristensen C.M. The future of the Microprocessor Business. IEEE Spectrum, April, 2002, P. 34-39. 2. Kartan A., Eilenberg S. Homological algebra. M., 1960. 376p. 3. Nilson N. Principles of atificial inetelligence. M.: Radio i svyaz, 1985. 373p. 4. General algebra. Reference. T.2. Skornyakov. Category.M.: Nauka. 1991. P.368-460. 5. Charles H. Roth Jr. Digital Systems Design UsingVHDL. Boston: PWS Publishing Company, 1998. 470 p. 6. Ashenden, Peter J. The designer's guide to VHDL. San Francisco, California: Morgan Kaufmann Publishers, Inc. 1996. 688 p. 7. SuvorovaE. A., Sheinin Yu. E. Digital systems design using VHDL. SPb.: BHV-Petersburg,2003. 576p. 8. Semenets V. V., Hahanova I. V., Hahanov V.I. Digital systems design using VHDL language. Kharkov: KhNURE. 2003. 492 p. 9. Bergeron, Janick. Writing testbenches: functional verification ofHDL models. Boston: Kluwer Academic Publishers. 2001.354 p. 10. Help system. Synplify Pro User Guide and Tutorial of Sinplicity. 256 p. 11. Bhasker J. A VHDL Synthesis Primer. Allentown: Star Galaxy Publishing. 1998. 296p. 12. GrushvickyR.I., Mursaev A.H., Ugrumov E.P. System design based on programmable logic devices. SPb.: BHV-Petersburg. 2002. 608 p. 13. Soloviev V.V. Digiral circuits design based on programmable logic integrated circuits. M.G Hot line-Telecom, 2001.636p. 14. KnushevD.A., KuzelinM.O. Xilinx PLD: general family structure description. M.: Publishing house "Dodeka-XXI", 2001.238p. 15.SamirPalnitkar. Verilog-VHD. A giud to digital design and synthesis. Sun Soft Press, Prentice Hall Title. 1996. 396 p.
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