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30
Семинары
научный семинар фтк
23 сентября 2011 г.
В рамках договора о сотрудничестве между Санкт-Петербургским государственным политехническим университетом и университетом Айзу (Япония) на факультете технической кибернетики состоялся научный семинар. Представляем аннотацию основного доклада семинара, с которым выступил Сайто Хи-роши (Saito Hiroshi), Ph.D., Assistant Prof., School of Computer Science and Engineering, University of Aizu.
Commercial VLSI circuits of the day are based mostly on synchronous circuits which are controlled by global clock signals. However, if the integration technology advances more and more, synchronous circuits meet the following problems. The first one is the clock skew caused by wire delays. The clock skew may result in synchronization failures. The second problem is higher power consumption. If clock signals are distributed to many components with high frequency, the power consumption on the clock tree networks become significant. Finally, there is electro-magnetic interference (EMI). This means that when a transition of clock signals happens, the current begins to flow. Thus, if many components operate at the same time, the peak current becomes large. This results in high levels of EMI.
In contrast to synchronous circuits, asynchronous ones are controlled by pairs of local handshake signals, so they have lower power consumption and lower EMI level because of the absence of global clock signals. However, the difficulty of asynchronous design is conditioned by that hazard-free implementation is required. In addition to this, the design method is sensitive to what the delay model, the control protocol, and the data encoding scheme have been selected. The asynchronous design support is not yet well developed in existing environments. As a result, there are few asynchronous solutions reaching the production stage.
In our research we propose the method of asynchronous circuits design automations aimed both to application-specific integrated circuits (ASIC) and field-programmable gate array (FPGA) models. We develop a series of tools for design automation which actually include the following components: behavioral synthesis tool allowing the conversion from C language model to register transfer level (RTL) model (through operation scheduling, resource allocation, and control synthesis), static timing analysis support tool for timing verification, and support tools for delay adjustment. The layout synthesis support tool (floor planner for performance optimization) and power optimization tools are in design. The future steps include development of a converter form synchronous circuits to asynchronous ones, communication synthesis tool, and tools for verification and testing.
H. Saito, V. Marakhovsky, E. Pyshkin
DESIGN automation For Asynchronous CIRCuITS
