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CJFET Differential Pairs Constructions and Characteristics for Design of CBiCJFet Differential Amplifiers and Differential Difference Amplifiers
Savchenko E. M.1'2'3, Drozdov D. G.1'3, Rodin V.GЛ3, Grushin A. I. \ Dukanov P. A.1, Prokopenko N. N.4'5
^SC "SPE "Pulsar", 2JSC "GZ "Pulsar", Moscow, Russian Federation 3MIREA - Russian Technological University, Russian Federation 4Don State Technical University; 6Institute for Design Problems in Microelectronics of RAS, Russian Federation
E-mail: prokopniklOJO&gniaiLcom
We have developed technology and construction solutions system to increase differential pairs (DP) of JFet with p- and n-channels identity, which are included into silicon complementary bipolar process of SPE "Pulsar" (Moscow). The possibility of creating several types of JFet DPs within the process is shown. The paper presents the results of experimental studies of two types of DP JFet designs with p- and n-channels for the spread of gate-source voltage AVgs depending on the drain current and drain-source voltage. The main features of the first design of p-cliannel JFet.s were the following: formation of drain/source area due to passive base of npn-transistor and deep collector areas for pup-transistor: channel formation based on p-layer collector of pnp-transistor; formation of bottom gate using p+ buried layer; top gate formation due to active base and polysilicon emitter of npn-transistor. A feature of the second JFet design was top gate formation due to passive base. The designs of the first and second types of n-channel Jfet. were formed similarly, taking into account the replacement of the applied areas of bipolar transistors with opposite ones in the type of conductivity.
It was found that with increasing drain current AVas decreases, and with increasing drain-source voltage AVgs at high currents increases for DP based on p-channel JFet with the first type of design. The maximum difference AVgs was in the range of 5-80 mV for a given differential pair JFet with a p-channel. On plots for DP p-channel JFet with the second type design a significantly lower voltage spread AVgs was shown: for example, for the drain current Id = 50 ^A the voltage spread AVgs did not exceed 10 mV. In this case the voltage spread AVgs practially did not depend on drain-source voltage in contrast to differenctial pair of the first type.
The second type JFet n-channel differential pairs like for the DP p-channel JFet provided lower spread values in comparison with the first type design: AVgs reached values of 5-20 mV. Moreover, for the design of the second type, a significantly weaker effect of the drain-source voltage on AVgs was observed at high current densities. The developed designs of differential pairs based on p- and n-channel JFet are recommended for use in organizing the production of CBiCJFet analog circuits, including operations at low temperatures.
Key words: p-n junction field-effect, transistors; differential pair; drain-gate characteristic; silicone complementary bipolar technology
DOI: 10.20535/RADAP.2019.79.71-77
Introduction
An identity of JFet differential pair (DP) at similar source currents is an important parameter, which characterizes a quality of JFet construction and corresponding JFet process fl 9]. This DP's property significantly influences zero-level of analog ICs. including operational [10 12] and instrumental [13] amplifiers, as well as errors of input low-noise [14 16]. chargesensitive [17.18] and transimpedance [19] amplifiers.
sources of reference current and voltage [20] and so on is a priority in the design of AM.
A process, developed by SPE "Pulsar" [21]. allows to design analog ICs. containing JFets and HF complementary bipolar transistors. But bipolar active elements (especially p-n-p) have extremely low values of base current gain in cryogenic temperatures range. So to build low-temperature and low noise sensor interfaces and input stage of corresponding special analog ICs it is appropriate to implement only on
Fig. 1. p-Chaririol JFets Differential Pair Topology
CJFet components. This limitation causes development problem for analog ICs' functional unit base CJFet, on base of which it is possible to develop different OA. continuously operating voltage stabilizers, current and voltage comparators, active ARC etc. Todays' level of CJFet's circuitry is very low and not developed. It causes a problem of CJFet analog OM circuitry, it is more compliacated than the one for CMOS and BJ processes. Its reason is different static voltage polarity between source and gate of JFet in active mode (comparing with drain-sonrce polarity). As a consequence the following is required firstly to design CJFet analog OM: special CJFet current mirrors (CM), which are not implemented per circuits traditional for CMOS and BJT, CJFet input differential stages, buffer amplifiers (BA) with source output, rail-to-rail CJFet BA, input stages of fast CJFet AM, intermediate folded cascode, static mode stabilizer circuit (reference current sources and potential offset circuit), operational amplifiers with increased gain, fast CJFet OA, micropower CJFet OA, differential difference amplifier, OTA amplifiers with controled slope etc. Conceptually we need updated concept for developing wide class of analog CJFet ICs, which practically were not developed because of dominant impact of cheap techology for CMOS and BJ and small production of low temperature microelectronic devices. However modern necessities of space instrumentation, high energy physics, medicine, quantum computing systems, high speed railway transport etc. stimulate development of this scientific direction. The above circuitry tasks are of high priority.
The methods to increase identity of JFet DP are connected with JFet rational construction and its implementation technology [21]. It is known that CBi-pCJFet process in BiConi3HV modification of Texas Instruments company [22, 23] allows developing new precision operational amplifiers OPA211 and OPA827 wth JFet and BJT, which combine nltralow level of noise coefficient and low power consnmtion. The said amplifiers are characterized by enabling parameters. BiConi3HV process makes possible to provide next generation of analog electronic component base, it includes all best microelectronic achievements. But
OPA211 and OPA827 operate at temperatures of-40°C and higher according to BiConi3HV process, which is provided by bipolar transistors application. It is not enough for several tasks.
The purpose of this article is to develop and describe process and construction solutions, which provide identity improvement for CJFet DP with p- and n-channels, integrated into silicon complementary bipolar technological process of SPE !'Pnslar" (Moscow).
1 p-Channel JFet Differential Pairs mady by SPE "Pulsar" and their Basic Characteristics
It is possible to develop several types of p-n-jnnction field-effect transistors (JFet) within silicon-based bipolar process. There is a topology of differential pair of n-channel JFets on Fig. 1. It includes the following sections: S-area source, G-area top gate, D-area drain.
The parameters of the first construction of p-channel JFets (Type 1) are the following:
development of drain/sonrce area duo to passive base of npn-transistor and deep collector areas for pnp-transistor, when a distance between drain/souce areas are 4.2 ^m;
channel development based on p-layor collector of pnp-transistor:
development of bottom gate using p— buried layer:
top gate development duo to active base and polysilicon emitter of npn-transistor.
There are drain-gate characteristics of p-channel JFets differential pair at 5 V and 10 V of drain voltage.
A dependence of drain-sonrce voltage nonidenti-ty AVqs from drain current is defined for the above contraction of p-channel JFets (Fig. 3). The Fig. 3 shows that AVqs reduces when current increases, and AVqs increases at high currents, when drain-source voltage increases. A spread of voltages AVqs does not go below 80 mV in a drain current rage up to 50 ^A.
There arc: drain-gate: characteristics of second type: p-channel JFets differential pair at 5 V and 10 V on drain.
Fig. 2. Dependence In = f (Uqs) at Uns = 5 V (a) and Uns — 10 V (b) for p-Channel JFet Differential Pair (Type 1)
The: parameters of p-channel JFET second construction (Type 2) are the following:
development of drain/source area due to passive base of npn-transistor and deep collector areas for pnp-transistor. when a distance between drain/'souce areas are 6.6 ^m;
channel development based on p-layer collector of pnp-transistor:
development of bottom gate using p+ buried layer:
top gate development due to passive base.
(b)
Fig. 4. Dependence In = f (Uqs ) at Uns = 5 V (a) and Uns — 10 V (b) for p-Channel JFet Differential
Pair
There IS à dependence of drain-source AVGs voltage spread on drain current for this pair of transistors.
Fig. 3. Dependence AVqs = f (Id ) at Uns — 5 and 10 V for p-Channel JFET Differential Pair (Type 1)
Fig. 5. Dependence AVqs = f (Id) at Uns — 5 V and 10 V for p-Channel JFET Differencial Pair (Type 2)
The Fig. 5 shows that the second type JFet differential pair has significantly smaller spread of voltages AVgs- For example, a voltage spread AVqs does not exceed 10 ^V for drain current In — 50 ^A. In this case the voltage spread AVqs practially does not depend on drain-source voltage in contrast to differenctial pair of the first type.
2 n-Channel JFet Differential Pairs made by SPE "Pulsar" and Their Basic Characteristics
There is a topology of n-channel Fets differential pair on Fig. 6. It includes the following sections: S-area - source, G-area top gate, D-area drain.
Fig. 6. n-Channel JFet s Differential Pair Topology
We investigated two types of n-channel JFets similarly to p-channel JFets: Tyep 1 top gate area based on active base of npn-transistors, Type 2 top gate area is developed based on passive base of npn-transistors.
There are drain-gate charactrisitics of n-channel JFets at 5 V and 10 V on drain for differential pairs of the first and second types on Fig. 7 and 8 correspondent!^
(b)
Fig. 7. Dependence Id = f (Ugs) at Uds = 5 V (a) and 10 V (b) for n-Channel JFET Differential Pair (Type 1)
(b)
Fig. 8. Dependence Id = f (Ugs) at Uds = 5 V (a) and 10 V (b) for n-Channel JFET Differential Pair (Type 2)
A cut-off voltage is Uto 3.2-1.7 V for n-channel transistors in comparison with Ut0 5.5-4 V for p-channel transistors. As a result there are smaller current of drain for n-channel JFet at similar area. Thus it is reasonable to compare these transistors at drain current of 10 ^A, but not at 50 ^A (as was done for p-channel transistors).
Dependence AVgs on drain current (Fig. ) for the first type n-channel transistors differential pair substantially similar to the difference of the first type p-channel JFet differential pair (Fig. 3). But there is significantly weaker influence of drain-source voltage for n-channel JFet at higher current density. AVgs for drain current Id = 10 mA does not exceed 30 mV.
Fig. 9. Dependence AVgs = f (Id) at Uds = 5 V and 10 V n-Channel JFET Differential Pair (Typel)
The values of voltage spread AVqs are significanly lower: from 5 to 21 mV for the second type n-channel transistors (Fig. ). AVqs is not higher than 8 mV at JD = 10 ^A. Similar to p-channel transistors (Type 2) there is an optimum value of drain current at which there is a minimum of AVqs- When the drain current increases any further, AVqs weakly depends on drain current value similarly to all considered types of differential pairs.
25
0 -"-"-'-
0 5 10 15
id(ma)
Fig. 10. Dependence AVqs = f (Id) at U^s — o V and
10 V for n-Channel JFET Differential Pair (Type 2)
So it is defined, that to provide minimum values of spread AVqs for JFet differential pair, including considerting low temperature influence, it is reasonalbe to use the second type of p-n junction complementary field-effect transistors construction.
Conclusion
We have developed constructions of p- and n-channel JFets, included into silicon complementary bipolar process of SPE "Pulsar", which provide relatively high identity of drain-gate characteristics at their differential input (Uos < 5^10 mV) and possibility to develop CBiCFet integral circuits.
Acknowledgments
The study has been carried out under the Russian Science Foundation Grant (Project 16-19-00122-P).
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Конструкщ!" i характеристики дифе-ренщальних пар CJFet транзистор!в для проектування CBiCJFet дифе-ренщальних i мультидиференщальних операцшних шдсилювач!в
Савченко 6. М., Дроздов Д. Г., Родгн В. Г., Грушин А. П., Дюканов П. О., Прокопенко М. М.
Розроблепо систему техполог!чпих i копструктив-пих р!шепь. що забезпечуе шдвшцеппя !дептичпост! диферепц!алышх пар (DP) польових трапзистор!в з ке-руючим р-н переходом (JFet.) з р- i n-капалами. що вбудовапих в кремшевий комплемептарпий бшолярпий техполог!чпий процес "НВП "Пульсар". Показано, що в рамках дапого техполог!чпого процесу можливс ство-решш дешлькох тишв DP JFet. В робот! представлен! результати експеримепталышх досл!джепь двох тишв копструкцш DP JFet з р- i 11- каналами з розкидом напруги затвор-вит!к AVgs в залежпост! в!д струму стоку i папруги ст!к-вит!к. До осповпнх особлнвостей першо! копструкц!! р-капалыюго Jfet. ставнлнся: фор-муваппя областей стоку / витоку за рахупок пасивпо! базн прп-трапзистора i областей глнбокого колектора рпр-трапзистора; формуваш1я каналу па основ! р-шару колектора рпр-трапзистора: формувашш пижпього затвору з застосуванням р+ прихованого шару; формувашш верхпього затвору за рахупок активно! базн i пол!кремп!евогох ем!тера ири-трапзистора. Особлшмстю друго! копструкц!! Jfet. було формуваш1я верхпього затвору впасл!док пасивпо! бази. Копструкц!! першого i другого тишв п-капалышх Jfet. формувалися апалог!чпо з урахуваппям замши застосовува1шх областей бшоляр-пих трапзистор!в па протилежш за типом пров!дпост!. Для DP па основ! р-капалышх JFet. з копструкгцяо першого типу встаповлепо. що з! зростаппям струму стоку величина AVgs знижуеться, а з! зб!льшенням напруги
ст!к-вит!к ДУсв за великих струмах зростае. Для дано! диферепц!алыю! пари JFet. з р-каналом максимальна р!зниця ДVGS лежить в межах 5-80 мВ. Для ОР р-капалышх JFet. з копструкц!ею другого тгшу наведено граф!кн. що показують !стотпо мепше зпачеппя розкнду напруг ДРсз: паприклад, для значения струму стоку 1в = 50 мкА розкпд напруг ДVGS не перевпщуе 10 мВ. При цьому. па в!дм!пу в!д першого типу ОР. розкпд напруги ДVGS практично не залежить в!д напруги ст!к-вит!к. Як ! для ОР р-капалышх JFet. диферешцальп! пари п-капалышх JFet. другого тгшу забезпечили мепш! зпачмшя розкиду в пор!впяпп! з копструкц!ею першого типу: ДVGS досягае зпачепь 5-20 мВ. Також для копструкц!! другого тгшу спостер!галося зпачпо славший вплив напруги ст!к-вит!к па ДVGS у раз! високо! щ!лыюст! струму. Розроблеш копструкц!! диферепц!аль-1шх пар па основ! р- ! п-капалышх JFet. рекомепдуеться використовувати при оргап!зац!! виробпицтва CBiCJFet. апалогових м!кросхем. в тому числ! для експлуатацп в умовах 1шзьких температур.
Клюноог слова: польов! трапзпсторн з керовапим р-и переходом: диферепгцальш пари: характеристика ст!к-затвор: кремшева комплементарна бшолярпа техполог!я
Конструкции и характеристики дифференциальных пар CJFet транзисторов для проектирования CBiCJFet дифференциальных и мультидиффе-ренциальных операционных усилителей
Савченко Е. М., Дроздов Д. Г., Родин В. Г., Грушин А. П., Дюканов П. А., Прокопенко П. П.
Разработана система технологических и конструктивных решений, обеспечивающая повышение идентичности дифференциальных пар (ОР) полевых транзисторов с управляющим р-п переходом рРе^ с р- и 11-капалами. встроенных в кремниевый комплементарный биполярный технологический процесс АО "НПП "Пульсар" (г. Москва). Показано, что в рамках данного технологического процесса возможно создание нескольких типов ОР JFet.. В работе представлены результаты экспериментальных исследований двух тгшов конструкций ОР JFet. с р- и 11- каналами по разбросу напряжения затвор-исток ДУсе в зависимости от тока стока и напряжения сток-исток.
К основным особенностям первой конструкции р-капалыюго ЛЫ относились: формирование областей стока/истока за счёт пассивной базы прп-трапзистора и областей глубокого коллектора рпр-трапзистора: формирование капала па основе р слоя коллектора рпр-трапзистора: формирование нижнего затвора с применением р+ скрытого слоя; формирование верхнего затвора за счёт активной базы и поликремпиевого эмиттера прп-трапзистора. Особенностью второй конструкции ЛЫ являлось формирование верхнего затвора за счёт пассивной базы. Конструкции первого и второго типов п-капальпых ЛЫ формировались аналогично с учетом замены применяемых областей биполярных транзисторов па противоположные по тгшу проводимости.
Для ОР па основе р-канальных JFet. с конструкцией первого типа установлено, что с ростом тока стока величина ДVGS снижается, а с увеличением напряжения
сток-исток AVgs при высоких токах возрастает. Для данной дифференциальной пары JFet с р-каналом максимальная разница DVGS лежит в пределах 5 — 80 мВ. Для DP р-канальных JFet с конструкцией второго типа приведены графики, показывающие существенно меньшее значение разброса напряжений AVgs- например, для значения тока стока Id = 50 мкА разброс напряжений AVgs не превышает 10 мВ. При этом, в отличие от первого типа DP, разброс напряжения AVgs практически не зависит от напряжения сток-исток. Как и для DP р-канальных JFet дифференциальные пары п-канальных JFet второго типа обеспечили меньшие значения разброса в сравнении с конструкцией первого
типа: AVgs достигает значений 5 — 20 мВ. Также для конструкции второго типа наблюдалось значительно более слабое влияние напряжения сток-исток на AVgs при высоких плотностях тока.
Разработанные конструкции дифференциальных пар на основе р- и n-канальных JFet рекомендуется использовать при организации производства CBiCJFet аналоговых микросхем, в том числе для эксплуатации в условиях низких температур.
Ключевые слова: полевые транзисторы с управляющим р-n переходом; дифференциальные пары; стоко-затворная характеристика; кремниевая комплементарная биполярная технология
