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УДК 658.512.2
A. Tetelbaum, М. Shanblatt CAD METHODOLOGY FOR BEHAVIORAL TO PHYSICAL LINKAGE
I. Introduction
Many current and emerging IC applications are extremely complex digital containing programmable and customized parts with very high requirements to theii parameters (cost, area, power consumption, and clocking frequency). To design such VLSIs the CAD methodology should support hardware/software co-design and include new tools that will allow to take into account system-level specification, hardware/software partitioning, concurrent design of hardware/software parts, methods for early prediction and evaluation of the layout, etc. In particular, a logical initial circuit design step should include an estimation of the required power consumption and chip area limitations [1]. Specifically, information of this type is needed to ensure
that the final physical layout is not only efTicirni in cite of chip real estate and wire length, but also provides a stable electnc.il selicme^ for minimum power consumption and clocking. Tipicnlly, behavioral models roniam lutlt or no information on real layout properties of physical inteivonnfcnonj: interconnections are all considered ideal, specified in a netlist described as uniilcss connections or nets, or. at best, they reuse estimated parameters from previous design.
The dominant overall design methodology today basically involves a behavioral modeling layout design verification iteration cycle [2] in which the physical correctness of a design can be seen only after the verification phase. Much improvement has been made to the verification phase. The industry has started moving towards a combination of prediction based on floorplans and back-annotation of layout information for more accurate characterization of layout effects on circuit performance and as a parameter for tuning structural circuit design. This strategy, however, lengthens the design cycle and number of design iterations by procrastinating the consideration of electrical effects [3].
An enormous design space needs to be explored before a good solution, particularly in terms of performance, can be found. This is a very time consuming process, so high level choices and early trade-off evaluation are extremely important. In a physical design system, a timing analysis is accomplished prior to layout design and can include some predictive capabilities [4]. The problem of evaluation of area tradeoffs for VLSI layouts has been explored based on an area prediction method using analytical and constructive models [5]. A well partitioned hierarchy, as measured by the associated Rent parameter, will correspond to an area-efficient layout [6].
2. A New Framework
Many physical parameters ultimately important to an adequate analysis are neglected at the behavioral modeling level. These parameters often include resistance, capacitance, inductance, cross talk sensitivity among lines, and the type of interconnection (for example, short or long, on-chip or chip-to-chip, MCM inter-chip, intra-chip, inter-layer, or I/O communications). Because of this, results produced by high level design tools may be functionally correct yet produce layouts which are nonfunctional due to unpredicted physical effects. The premise of this paper is that a methodology for high level design that includes models of physical effects, and for layout design incorporating high level recommendations based on realistic layout estimation, will produce more reliable physical layouts.
The dominant design methodology today involves a behavioral modeling - layout design verification iteration cycle [6]. Thus, functional correctness seen at the behavioral stage may translate to nonfunctional layout resulting in the necessity to repeat the entire cycle - perhaps several times. It is asserted that a more effective paradigm would be to establish a distinct behavioral design cycle which includes two main procedures: an analysis/simulation phase and prediction phase.
During the analysis/simulation phase, classes of nets and modules pan be identified by using a newly defined set of metrics. These metrics can include classification of nets into categories such as essential nets (e.g., those critical to achieving the desired circuit performance parameters), noise producing nets (e.g., those which carry the high frequency clock and data lines), noise sensitive nets (e.g., those which must be physically isolated due to noise sensitivity such as low power nets or those sensitive to parasitic effects), and common nets.Also, classifications may be made on the basic of interconnection materials (metalization, diffusion, polysilicon) and geometry (widths, rectilinearity, and others). It is anticipated that many nets will fall into multiple categories such as essential and noise producing or essential and noise sensitive and thus will rise to the top in the hierarchy as "placement critical" nets. The same strategy can be similarly defined for modules in guidance of the placement problem. In addition to the classification aspcct, the
t
analysis/simulation phase will involve the definition or constraints and recommendations, in the form of methodology, for physical layout. The recommendations then guide the subsequent layout stages in t^rms hierarchically partitioning the layout from the most crucial elements down tp the common elements and dictate the choice of appropriate routing and placement algorithms and initial guesses for such algorithms. Moreover, if unacceptable simulation results or layout recommendations are discovered, design changes can be made very early in the process saving design time by minimizing design loop iterations.
During the prediction phase of the behavioral cycle, estimations of the main layout parameters (module sizes and numbers, interconnection lengths, chip area requirements, ets.) can be obtained. Also, this technique will enable the evaluation of more realistic expected performance parameters, such as throughput, critical path delay, and the like. Physical results, e.g., power consumption and thermal generation can also be estimated. And, on the basis of these advanced predictions, layout design and fabrication costs can be estimated. Cost analyses can be performed and cost corrections can be facilitated early in this design process [7]. This is all possible since new information which can be extracted at this phase will provide a clearer image of future layout one with much more information for cost prediction and help in streamling .the subsequent layout procedures. Finally, this image the layout estimation represents a significant enhancement to the design methodology in that it is a realistic prediction of the final layout and can be used as a comparative benchmark during layout design.
Unique to our approach is that a generalization of Rent's rule and the results of the analysis/simulation component can be combined to increase the accuray^f the final predictions. On the basis of this estimation, new metrics of layout Complexity can be derived. The layout complexity metric, assesing the degree of complexity of layout design relating to a desired level of performance, will be a prescription/recommendation for algorithm/tool choice at the physical level. This will lead to a matching of time spent^on layout to the complexity or’desired performance level of the circuity Utilizing these predictions, the electrical parameters on interconnections can be calculated and the analysis/simulation component can be repeated until desired parameters are obtained.
A second salient feature of this methodology is that linkage to physical layout will be naturally facilitated. Since these new metrics will have beeiv incorporated in the behavioral design stage, long iterations of th« design cycle'»» eliminated. More importantly, this methodology provides a mechanism fof^m£prporatin^ the essential parameters necessary to design high speed low power circu'twnore efficiently by considering these effects eariy in the design cycle rather than at the latter stages of physical design. Thus, physical design will be faster, yet include more inherent and precise information on the fundamental electric characteristics of the nets and modules.
Layout design is traditionally decomposed into three main aspects: partitioning, placement, and routing. In this proposed methodology, the partitioning task will be modified by two developments. First, the layout complexity measure as defined above can be used as the major objective function. This will serve as a link, and in a sense, insurance, that the ultimate layout conforms to desired performance criteria. Secondly, the formulation of the problem is no longer a traditonal partitioning situation but is actually a reconstruction of the hierarchical functional structure to a hierarchical layout structure based on new considerations. Thus, the layout problem dimension is reduced and useful features of the functional structure can be extrapolated into the layout structure.
Placement and routing have generally been somewhat separated, due primarily to their combined complexity. Moreover, when advanced electrical effects are considered, the complexity worsens, with the number of placement-routing iterations increasing without any strengthening of the convergence guarantee. Our
proposed methodology addresses this problem by introducing a systematic set of layout abstractions (models and metrics). It is asserted that, even though more information is to be considered during layout, our overall strategy will tend to reduce layout design time. This is due to the evolutionary and hierarchical approach to generating layout.
As the layout progresses from very simple to increasingly complex models, rapid comparisons are made at each step between the current solution and the layout estimation found during the analysis/simulation stage. Essential differences identified at any step force a redefinition of the layout- model, or a backtracking to change the logical design or layout estimation on the basis of some newly discovered information. Additionally, since beginning stages use very simple models, time is not wasted before an inconsistency is discovered. The solution found at each step is done using minimal constraints appropriate to that level; it is then used as a seed solution for the next step, hence the evolutionary concept of layout emerges. When an overabundance of constraints are considered all at once, these constraints have a more profoundly coupled impact on system-level and layout-level design performance. This was demonstrated in [8] where global and detailed routing of macro-cells was studied.
Layout will be more efficient if viewed fundamentally as a stepwise refinement process. During the process, a layout model is gradually refined from a rough abstract model to an exact description meeting all specifications. By gradually refining the granularity of the Optimization method, a solution close to the global minimum can be achieved and appropriate constraints can be Introduced at the appropriate level.
The systematic models can be effectively represented in a characteristic matrix form providing a simple, but a comprehensive, view of Hayout model combinatorics. This systematio form will facilitate rapid analysis, use the traditional metrics, include the metrics extracted in the modified behavioral design phase, and, finally, can incorporate existing 2-D or future 3-D abstractions. Each model describes a layout with increasing accuracy taking into account more complex aspects and constraints. The set of all models and possible transformations among models defines the space of the layout problem. Then, solving the layout problem involves finding an optimal path from initial (simple representation) to the final geometric model in the space refining the level of realistic detail at each evolutionary step. The final model eventually includes all advanced information which has been considered from the initial phase of behavioral design. Each transformation corresponds to sofVing some aspect of layout problem, such as placement, pin assigment, floorplanning, global routing, and s6 on.
3. Conclusion
This paper present some rtew ideas for a conceptual model for enhancing the knowledge-based linkage between high-level modeling (behavioral, functional, and electrical) and the physical design of digital and analog VLSI circuits. The objective is to lay the groundwork for a new methodology which includes abstractions and metrics that lead to more efficiently defined and utilized CAD algorithms and tools. This new methodology can incorporate important improvements in handling the electrical and physical effects unique to this class of circuits.
Circuit families which can benefit from this improvement include moderate to high speed, low power analog and digital circuits with clock rates greater than SO MHz, perhaps up to 100 MHz. In many applications in this high performance area, dramatically reduced power dissipation is a design requirement. For example, this category includes portable computational and communication electronics, and medical devices, particularly implants. The technology base supporting these applications is multidimensional (2-D or stacked 3-D) hybrid ' wafer scale integration (multi-chip modules) using current or advanced thin films. This technology has the potential to deliver improvements in power management, low voltage
operation, low cross talk interconnects, and clock frequencies. The model proposes the development of new methodologies, abstractions, and metrics that lead to more efficiently defined and utilized CAD algorithms and tools. These new
methodologies incorporate significant improvements in handling electrical and physical effects which are ultimately important in producing efficient, reliable layouts yet are currently ignored in the process. This will be accomplished by defining a new behavioral to physical design relqtionship (linkage) and developing a more useful set of heuristic metrics related to electrical characteristics which have an impact on layout. In doing so, the methodology-also indicates a measure of layout complexity which can be estimated early on in the behavioral modeling process.
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