CC BY
14
Power Stations, Grids and Systems
UDC 621.3 https://doi.Org/10.20998/2074-272X.2021.4.07
A. Boussaid, S.E.I. Chelli, A.L. Nemmour, A. Khezzar
AN EFFECTIVE CONTROL ALGORITHM FOR DYNAMIC VOLTAGE RESTORER UNDER SYMMETRICAL AND ASYMMETRICAL GRID VOLTAGE CONDITIONS
Introduction. Voltage sag, which is associated to a transitory drop in the root mean square voltage characterizing an electrical source network. During these perturbations, the corresponding electronic customers and devices will suffer from serious operating troubles causing dangerous damages. Purpose. In order to attenuate this disturbance effects, the Controlled Dynamic Voltage Restorer constitutes a very interesting solution among many others that have been proposed. The novelty of the proposed work consists in presenting an enhanced algorithm to control efficiently the dynamic voltage restorer when voltage sag is suddenly occurred. Methods. The proposed algorithm is based on an instantaneous phase locked loop using a multi variable filter to synthesize unitary signals involved in compensation voltages computation relative to the sag apparition. Practical value. A detailed study concerning typical voltage sag, which is consolidated by simulation and experimental results, is conducted to show the used algorithm's effectiveness to cancel the corresponding voltage sag. References 44, table 1, figures 16. Key words: dynamic voltage restorer, power quality, voltage sag, phase locked loop, synchronous reference frame.
Вступ. Провал напруги, який пов 'язаний i3 тимчасовим падтням середньоквадратичноi напруги, характеризуе мережу джерел електричног енергп. nid час цих збурень eidnoeidHi споживачi (електронн припади та iншi пристрог) будуть страждати eid серйозних проблем у ант експлуатаци, що спричиняють небезпечн пошкодження. Призначення. Для того, щоб послабити вплив цих збурень, контрольований динамiчний вiднoвник напруги видаешься дуже щкавим ршенням серед багатьох тших, ят були запропоноваш. Новизна запропонованог роботи полягае у представленн вдосконаленого алгоритму ефективного управлтня динамiчним вiднoвникoм напруги, коли раптово вiдбуваеться провал напруги. Методи. Запропонований алгоритм базуеться на миттевому фазовому замкненому кoнтурi з використанням багатoварiантнoгo фыьтра для синтезу унтарних сигналiв, що беруть участь у обчисленн напруги компенсаци стосовно прояву провалу. Практичне значення. Детальне до^дження стосовно типового провалу напруги, яке узагальнено за допомогою моделювання та експериментальних результатiв, проведено, щоб показати ефективтсть використовуваного алгоритму для лiквiдацii вiдnoвiднoгo провалу напруги. Бiбл. 44, табл. 1, рис. 16.
Ключoвi слова: динамiчний виновник напруги, яккть електроенерт, провал напруги, фазовий замкнений контур, синхронна система ввдл^.
1. Introduction. Power distribution system is an irreplaceable thing. Indeed, it should provide energy for costumers in an ideal sinusoidal form. For that, the number of connected equipments to the power network still increasing but that fact imposes critical problems to the network [1-3]. Poor power quality outcomes in financial losses which has a major harmful impact on the economical industry sector.
The voltage quality issues is more important in comparison to sensitive loads which requires to be supplied cautiously, regarding to the previous mentioned problem, it consist mainly in voltage sags and swells, voltage harmonics, current harmonics, fluctuations (flickers), frequency variation and unbalance [4-7].
Voltage sag has been widely studied in a considerable research papers, which is defined as temporary decrease in the root mean square voltage between 10 to 90 % of nominal voltage, for a duration interval of 0.5 cycles to one minute as it's presented in IEEE 1346, IEEE 1159 and IEC 61000-2-1 standers [8, 9]. By way of explanation it is characterized by a sudden reduction of nominal voltage from 0.1 to 0.9 per unit followed after a short period of time by a voltage recovery. According to the mentioned standards, normal voltage sag takes from 10 ms to 1 minute.
Voltage sags caused mainly by large induction motors starting or by different faults related to power system. Consequentially, sensitive loads and a significant number of electronic devices could be malfunctioned or completely deteriorated as a result for voltage sag occurrence. Hence, huge losses at costumer loads are take place.
Voltage swell is defined in the previous mentioned IEEE standard as an increase in the root mean square (RMS) supply voltage from 1.1 to 1.8 per unit for duration from 0.5 cycles to 1 min. Voltage swell are mainly due to large capacitors switching or connecting / disconnecting of heavy loads. Voltage swells are less widespread in distribution network, for that reason, they are not as important as voltage sags [10-14].
The above mentioned issues related to power quality has opened up a discussion on possible solutions to overcome these problems. Researchers have proposed a large number of custom power devices (CPDs). The most effective one is to use compensators based on power electronic devices.
These compensators could be in series, shunt or hybrid form. Literature is rich by numerous classifications of CPD [15], Based upon its structure, various custom power devices are usually classified into three categories: unified power quality conditioners (UPQC), distribution static compensator (D-STATCOM) and dynamic voltage restorer (DVR).
Using series or shunt power filters in separate may not be the wanted preferred solution. For this reason, the device named UPQC [16, 17] performing both functionalities of series and shunt active filter is introduced and its concept is developed [18, 19].
The D-STATCOM is another choice for solving voltage unbalance, and power quality enhancement. It maintains the voltage sag at the desired reference by supplying or receiving the reactive power in the distribution
© A. Boussaid, S.E.I. Chelli, A.L. Nemmour, A. Khezzar
network. This compensator has been deployed in a three-phase four-wire distribution system [20].
Another alternative based on series custom power compensation could ensure a high quality voltage purpose [12, 13]. DVR is composed of a dc-energy storage system, a voltage source converter, an output filter and a coupling transformer.
The performance of the abovementioned CPDs is related mainly to the control algorithm of each device. Indeed, researchers pay a great attention to the algorithm strategies. Instantaneous Symmetrical Components Theory (ISCT) generates reference waveforms to balance a given load [21, 22]. Instantaneous Power Theory is introduced to compensate voltage faults in a dynamic way in the time domain based on PQR transformation [23]. Adaline (Adaptive linear element) control strategy is an Artificial Neural Network (ANN) that is used to control a capacitor supported DVR for power quality enhancement [24]. Space Vector PWM Strategy is presented in [25] to control a modified DVR composed of a conventional three phase voltage source inverter and an emitter follower. Synchronous Reference Frame Theory [26] is one of the most used algorithms to generate reference signals; its operating principle is based mainly on converting the load voltages to the rotating reference frame using the Park's transformation with unit vectors derived by a phase locked loop (PLL).
Detecting the grid phase angle and frequency in a fast and accurate way is the key of a good synchronization process. Several synchronization methods have been proposed in literature; the method based on detecting the zero crossing point of the grid voltages is characterized by a large synchronization time. In addition, it fails in detecting that point in case of grid frequency variation and unbalanced voltages.
The algorithm based on afi stationary reference frame conversion [27] is another alternative to detect the grid phase angle and frequency. The algorithm performances are related mainly to the intrinsic filter parameters that affect the algorithm dynamic response under asymmetrical grid faults conditions.
In three phase application, the phase locked loop (PLL) is the most used strategy where the synchronous reference frame (SRF) based PLL constitutes the common configuration [28-30]. It based on transforming the three phase voltages from abc frame to synchronous rotating reference frame using Park's transformation in order to identify the grid angle and frequency quantities.
Synchronous Reference Frame is known as a feed forward open loop control strategy. It is characterized by its simplicity and stability. Their main inconvenient is expressed in poor transient response and possibility offset error at the steady state because of voltage drop on the injection transformer and the series branch of the filter. To overcome these problems, feedback controllers are used. Feedback control process consists of measuring the DVR output voltages and fed back to the controller voltages. A variety of controllers have been presented in literature such as proportional, Proportional-Integral (PI), Proportional-resonant (PR) [31, 32], fuzzy controller [33, 34], H»
controller [35], sliding mode controller [36-38], state variable controller [39], predictive and repetitive controllers [40-42], feedback linearization [43].
The goal of the paper is the investigation of an effective phase locked loop to generate unitary signals that contain the fundamental voltage phase angle information used in calculating compensating voltage in case of a voltage sag occurrence.
Subject of investigations. The introduced PLL is compared to the conventional one in simulation and experiment. After that, controlling the DVR by the proposed algorithm is accomplished to show the effectiveness of the algorithm.
This paper is structured as follows: Section 2 describes the Dynamic Voltage Restorer Configuration topology with its operating principle with respect to sudden voltage sags occurring. Section 3 presents the control algorithm explaining both conventional phase locked loop topology and the proposed one. Section 4 discusses the obtained results through simulation and experimentation studies. Finally, a conclusion relative to the obtainable work is presented.
2. DVR Configuration Topology. A dynamic voltage restorer is generally connected in series with the protected load through a transformer. A DVR generates voltage references to be added to those of the grid in order to compensate the voltage disturbance at the load side. The schematic configuration of a typical DVR is presented in Fig. 1, which contains the following elements:
Fig. 1. DVR Schematic Topology
1) Energy storage device: commonly called DC bus side, it allows the voltage source inverter to provide the power grid by the reference generated voltages via the transformer. It could be batteries, capacities or even photovoltaic panels.
2) Voltage Source Inverter (VSI): a voltage source inverter is a power electronic configuration fed by the previously mentioned energy storage device to regenerate the desired sinusoidal voltage references. Recently, the switching configuration of the Voltage Source Inverter is based on IGBT. Nevertheless, peaks due to the switching process are eliminated by passive elements such as resistance R, inductance L, and a capacitance C at the VSI output.
3) Injection transformer: the main purpose of this transformer is to inject the generated voltage references to
the power grid which is connected by its high voltage side, whereas, the low voltage side is connected to the DVR power circuit.
4) Control strategy: control algorithm is considered as DVR heart. definitely, it detect the voltage disturbance and generate a voltage reference in phase to those of the grid and control the Voltage Source Inverter by generated voltage in feedback control in order to compensate the occurred voltage disturbance.
DVR could be expressed in an equivalent circuit (Fig. 2). It consists of a source voltage Vs delivering a current Is, the source reactance is defined by Xs. The considered source is feeding two identical loads ZA and ZB passing through a feeder for each load FA and FB, each feeder has a reactance xA and xB respectively.
V = V — IX ■
' pre—sag ' s 1 s ■
Is = Ia + IB =-
Vp
Vp
Z A + xA ZB + xB The current through ZA and ZB is the same because of the identical impedances in healthy conditions. At the occurrence fault time on the first feeder, a high circuit current will flow to the broken feeder, on the other side, the current of the second feeder will be reduced. Therefore, the voltage of the second feeder will be decreased as well. This voltage drops is defined as voltage sag. At that point, the source current Isfault and voltage sag Vsag are defined as:
Vsag Vs IsfaultXs ;
I
Vs
sfault
sag
Vs
sag
(3)
(4)
Fig. 3. Equivalent circuit for DVR voltage injection calculation
Fig. 2. Equivalent circuit for voltage sag calculation
From the equivalent circuit and basing on Kirchhoff's Law, voltage Vpre-sag and current Is in case of healthy power grid at the point of common coupling are given by:
(1) (2)
a b
Fig. 4. Phasor diagram for: (a) voltage sag compensation; (b) voltage swell compensation
3. DVR Control Strategy. The DVR compensates voltage sags by injecting or absorbing reactive power or real power [44]. Reactive power is injected when the DVR voltages are in quadrature with the currents with respect to fundamental frequency, at that point, DVR relay on a self supported dc bus. Nevertheless, active power is injected when the DVR voltages are in phase with the current, thereupon, the need of a battery at the DC bus is necessary.
The voltages references are used to generate the IGBTs gate pulses for the voltage source inverter in a synchronous reference frame. The schematic corresponding to the SRF theory is shown in Fig. 5.
Firstly, source and load voltages are sensed and transformed to a stationary references frame using Concordia transformation as follow:
+1
vsa = XVsah sin(®t + $sah X h=—1
+1
xA ZB + xB Thus, DVR must be inserted between the point of common coupling and the sensitive load where the voltage sag takes place. Figure 3 illustrates the DVR placement process.
Most of disturbances in power grid are related to voltage sag and swell. Decreasing and increasing of voltage amplitude at the load side are accompanied by a phase angle jump, for that, control strategies must be adopted to compensate this issue in a very fast way in order to avoid losses of power supply. Figure 4 shows the phasor diagram for a DVR compensation in both voltage sag and voltage swell.
Z2n
Vsbh sin(®t + 0sbh — —X h=—1 3 +1 2n
vsc = X Vsch sin(®t + 0sch + -fX h=—1 3
(5)
v
+1
La ~ XVLah sin(®t + h=—1
+1
Z2f
VLbh sin(®t + fabh — —X h=—1 3 +1 In
vLc = X VLch sin(®t + hch + 2Г), h=—1 3
(6)
+
where: Vsah, Vsbh and Vsch are the voltages source amplitudes; VLah, VLbh and VLch are the voltages load amplitudes; $sah, $sbh and $sch are the voltages source phase angles; $Lah, $Lbh and $Lch are the voltages load phase angles; m is the voltage fundamental pulsation.
vsß_
vLa vLß
1 -1 -1 2 2
2 2 _
1 -1 -1 22 V3 V3
0
2
2
vsa vsb vsc.
vLa vLb .vLc.
(7)
(8)
vsd _vsq
vLd vLq
cos 9 sin 9
- sin 9 cos 9
cos 9 sin 9
- sin9 cos9
vsß
vLa vLß
(9)
(10)
\vDVRd - vsd - vLd;
vDVRq - v.
sq
~ vLq •
(11)
Since the voltages are converted to a stationary reference frame, the unit vector derived through a phase locked loop is taking in account to transform these voltages to a synchronous reference frame using Park transformation:
a b
Fig. 6. Phasor diagram exhibits the relation between abc frame (a) and dq frame (b)
Consequently, the DVR reference voltages are obtained by:
Jv DVRd - v sd - vLd ; ') * *
I v DVRq - v sq - vLq •
(12)
A controller is used to minimize the error between actual DVR voltages and the generated reference voltage. Lastly, DVR reference voltages are obtained in abc reference frame by applying the Concordia inverse transformation and Park inverse transformation as follow:
Figure 6 shows the phasor diagram of synchronous transformation. The afi coordinates are orthogonal axes obtained from the abc frame. The dq synchronous frame is obtained by rotating the the afi coordinates.
The reference load voltages (v La, v Lb, v Lc) are transformed to a synchronous reference frame as well in the same way. In the meantime, the DVR voltage along dq frame could be expressed by:
*
v DVRa
v DVR
ß
*
v DVRa *
v DVRb *
v DVRc
cos 9 - sin 9 sin 9 cos 9
1 °r -1 Û.
2 2
-1 £
.2 2 .
*
v DVRd
DVRq
v DVRa *
v DVRß
(13)
(14)
The three phase voltages system. The balanced three phase voltages system which takes into account any type of distortion can expressed by:
v
v
v
vsa = SVh sin(hmt +fa );
h=-œ
+œ
2n
vsb = S Vh sin(hmt + fa ——X
h=-œ
+œ 2n
vsc = S Vh sin(hmt + h + —>
(15)
h=-œ
The three phase distorted currents form could be represented as follow:
XIh sin(hct + );
h=-xi
*sb =X Ih sin(hct + 9h ——X (16)
h=-xi
S Ih sin(hmt + çh + —X
h=-œ
where: h denotes the order of the inverse, homopolar and direct harmonic components in the voltage or current systems; Vh, Ih, and qh are the amplitudes and phase angles of the harmonic components of the voltage and current systems respectively; c = 2xfs is the fundamental pulsation of the voltage or current systems.
Phase Locked Loop. Conventional Phase Locked Loop. A PLL principal is based mainly on Park transformation, beyond that, if the instantaneous derivative angle involved in Park transformation is equal to the three phase voltage pulsation system, the components along dq axes will be constant.
The block diagram of a typical PLL is shown in Fig. 7, it contain a phase detector (PD) in order to perform a comparison between the input signal and the arrived one from the Voltage Controlled Oscillator (VCO). Low-pass filter (LPF) is used to correct the error at the PD-output.
Fig. 7. Typical phase locked loop block diagram
The PLL consider the utility voltages expressed by Eq. (5), then, it goes to a synchronous frame passing by stationary frame using Eq. (7) and Eq. (9). After all calculation, the obtained equation is given by:
\vd = Vs sin(0-Omes ); \vq = Vs cos(0-Omes ).
(17)
From Eq. (17) one can notice that, if the phase angle error 0^ = 0 - 0mes is small, than this equation becomes:
vd = Vs (6-6mes ).
(18)
At the moment 0 = 0mes, the PLL is locked, on the other hand, if 0 ^ 0mes, the phase error is governed by a controller adjusting a until 0 = 0mes.
To accomplish the above explained phase lock, we consider the following block diagram of the locked loop as shown in Fig. 8.
Fig. 8. Three phase PLL structure diagram
Proposed-Phase Locked Loop. The main purpose of any PLL configuration is to generate a unite vector containing the utility phase angle in order to pass to a synchronous reference frame. The proposed configuration is based on a Multi Variable Filter (MVF) to generate a sin and cos unite vectors directly that contain the utility phase angle information.
The transfer function of the MVF is based on 'Hong-Seok-Song' work. Its formulation is expressed by the following equation
~a(s) = ^ + k) 2 xa(s) -
kmc
R(s) =
22 (s + k )2 + mc
k (s + k ) 2 2 (s + k ) +a£
22 ( s + k )2 + mc
R(s);
R(s) +
kmc
(19)
2 2 -a
(s + k ) +a£
xa (s)
where xa, xfi are the input signals and xa, are the
fundamental output signals.
From its formulation, the MVF filter is similar to a band-pass filter in the output response. Conversely, the integral effect of the MVF is neglected because it does not introduce a phase shift to the output signal regarding to its input. By way of explanation, both input and outputs MVF's signals have the same phase angle.
The developed analytical formulation of Eq. (19), could be given by:
S
h=-<» ^ + | (1 - h)m
sinl hmt + + a tan
(1 - h)m k
- e kt sinl hmt + <ph + a tanl (—
(20)
xR = -, —
I hS
h=-™ ^ + l (1 - h)m
cosl hmt + q>h + a tan
(1 - h)m k
-kt it l (1 - h)m - e cosl hmt + q>h + a tanl-
Eq. (20) shows that the MVF effectiveness in cancelation any kind of disturbance is related principally to the constant k. Indeed, it is obvious if k is taken small, the disturbances will be attenuated perfectly. Otherwise, the transient time response will increase in parallel which is explained by the exponential part. In this case, taking k so small, Eq. (20) takes the following form:
(1 - e-kt )sin(mt + Çl ); x R = — J3 (1 - e -kt )cos(mt + ^ ).
(21)
The concept is to hold back the voltage disturbance as possible in order to get a correct phase angle information which lead to a correct DVR control. A unit vector is obtained instantaneously without any phase
sc
I
h
a
2
k
I
h
2
k
shift by taking k so small, the negative aspect of large time response is defeated. The unit vector is defined by Eq. (22):
1
~a(( ) = sin(t + qi);
X 2 + 7 2
X„ + X/}
,(' )
■ = cos(t + q>1 ).
P
-400
0,00
0,05
0,10
0,15
1,5 1,0
tin
2 0,5
m 0,0 >>
Π-0,5
time (s)
0,00
0,05 0,10 (a.1)
0,15
0,00
0,02 (a.2)
0,04
1,5
1,0
^ 0,5 CT
en 0,0 ^
CO -0,5
-1,5
0,00
0,05 0,10 (b.1)
0,15
0,00
0,02 (b.2)
0,04
from t = 0 s to t = 0.01 s, which is totally acceptable under these sever unbalance conditions as shown in Fig. 10,b.2.
400
(22) %
4. Performances of the proposed PLL. To examine the proposed PLL performances, several tests have been accomplished. In the first case, a balanced three phase source voltages are considered as presented in Fig. 9.
From Fig. 9,a.1 and Fig. 9,b.1 one can notice that, the classical and proposed PLL have similar behavior where they produce suitable unit vectors, it is obvious from the presented phase angles as shown in Fig. 9,a.2 and Fig. 9,b.2.
400
-400
0,00
0,05
0,10
0,15
time (s)
1,5 1,0
_ 0,5
Ï?
№ 0,0 ^
Π-0,5
£Z
3-1,0
3-1,0 •
0,05 0,10 (b.1)
0,02 (b.2)
Fig. 10. Simulation results, Case 2: Unbalanced source voltages
The three phase source voltages are considered balanced and distorted by injecting the third and the fifth harmonics in the main voltages defined by the following equations:
va = Va1 sin(t + Val) + Va3 sin((t + *Pa3 ) + + Va5 sin(5ot + Ç>a5 );
Fig. 9. Simulation results, Case 1: Balanced source voltages
The second case of study takes unbalanced three phase voltages without harmonics expressed in a total mitigation of voltage phase as shown in Fig. 10.
In this case, the classical PLL fails in extracting the sin and cosine signals from the unbalanced source voltages as presented in Fig. 10,a.1, this fact leads to a phase angle shifting from its reference as illustrated in Fig. 10,a.2.
On the other hand, the proposed PLL still give pure unit vectors in Fig. 10,b.1, with a soft phase angle shifting
vb = Vb1 sin^®t + Vb1 -+ Vb3 sin^3®t + %3 - y) + + Vft5sinl 5at + qb5 -
3 2n 3
(23)
vc = Vc1 sin^®t + Vc1 + 2fj + Vc3 sin^3at + Vc3 + I + 2n
+ Vc5 sin| 5at + Ç>c5 +— |.
Figure 11 describes the three phase distorted voltages. From Fig. 11,a.1 and Fig. 11,a.2 it is clear that the classical PLL exhibits poor capacities in extracting the unit vectors containing the phase angle information. Otherwise, the proposed PLL still present high capability in giving an instantaneous unit vector even the presence of harmonics in the three phase source voltages as illustrated in Fig. 11,b.1 and Fig. 11,b.2.
400
CO
-400
Ç?
to 0,0 ^
to -0,5
3-1,0
-1,5 0,
1,5 1,0 _ 0,5 en 0,0 tö -0,5
time (s)
2
tfi 1 JD CT c
tO 0
<u tn to
-1
I ------R ....... eferenc ^lassica e ... l-PLL '
\ \ \ V
1 1
0,05 0,10 (a.1)
-2 0,00
0,02 (a.2)
to
J -1,0
0,00
0,05 0,10 (b.1)
0,15
2 0,00
0,02 (b.2)
0,04
Fig. 12. Experimental platform
Table 1
Experimental parameters
vs Vdc Cdc If kmvf
110 V 300 V 1100 ^F 4 mH 0.0001
200
tO
<U 100
CT
(0
§ 0 a)
O
3-100
o
to
-200
0,00
0,05
0,10
0,15
1,5 1,0 ^ 0,5 en 0,0 <0-0,5
£Z
3-1,0
time (s)
2
ai 1
JU
ro
c
<0 0
<u tn <0 .£=-1
-2 0,00
-1-!- Classical-PLL
\ \ \ \ *
A \ \ y
■ \ \ \ \
0,02 (a.2)
U) 1 JD CT £=
to 0
O) to to
-1,5 0,00
MVF-PLL
\ \ \ \ ■
A \ \ y
■ \ \ \ \
-2 0,00
0,02 (b.2)
Fig. 11. Simulation results, Case 3: Balanced distorted source voltages
Experimental validation. The proposed method performances are verified through simulation and experiment validations using Dspace 1104 platform as shown in Fig 12. Hardware parameters and control parameters used in experimental test are summarized in Table 1.
Figure 13 presents the balanced three phase voltages. In this case both classical PLL and the proposed one success in extracting unitary signals that contains the phase angle information as shown in Figs. 13,a.1, a.2 and Figs. 13,b.1, b.2.
0,05 0,10 0,15 (b.1)
Fig. 13. Experimental results, Case 1: Balanced source voltages
Figure 14 shows unbalanced three phase voltages expressed in taking-off the second phase. One can notice that, the classical PLL fails in extracting unitary signals as shown in Fig. 14,a.1 which leads to certain loss of phase angle information as presented in Fig. 14,a.2. On the other hand, the proposed MVF-PLL is motionless to this kind of unbalance and gives acceptable unit vectors and phase angle quality as shown in Fig. 14,b.1 and Fig. 14,b.2.
The last test is based on generating harmonics on the three phase source voltage as it generated in the simulation section. It is clear from Fig. 15 that the source voltages contain a huge amount of harmonics which weaken the classical PLL in extracting fundamental phase angle as shown in Fig. 15,a.1 and Fig. 15,a.2. Where, the MVF-PLL preserves its capability in giving true information in experiment tests as in simulation.
The aim of the second section of experimental study is dedicated to examine the dynamic voltage restorer under various conditions. Indeed, the first case is expressed in introducing a voltage sag in one phase by inserting a resistor in that phase in order to have the desired sag from t = 8:27 s to t = 8:44 s as it is shown in Fig. 16,a.1. The reference component required to compensate that sag is presented in Fig. 16,a.2. It is clear that, the DVR hits in rejecting the introduced voltage sag perfectly as it is illustrated in Fig. 16,a.3.
0,00
0,15
0,04
0,15
2
u>
<D 100
CT
(0
g 0
0) O
■3-100 o
to
-200
0,00
1,5 1,0
tin
2 0,5
to 0,0 >>
(0-0,5
-1,5
0,05 0,10
time (s) 2
0,15
0,00
0,05 0,10
(a.1)
1,5 1,0
¡-0,5 c ^-1,0
0,05 0,10 (b.1)
(fl 1 £=
TO 0
<L>
U)
to
1
Classical-PLL
1
1
\
0,15
0,00 0,02 0,04 0,06 0,08 (a.2)
tn 1 ju
c
to 0 <u
-1-!- MVF-PLL
\ \ ^ ■
\ \ \
\ \ \
-2 0,00
0,02 (b.2)
Fig. 14. Experimental results, Case 2: Unbalanced source voltages
-200
0,00
0,05
0,10
0,15
time (s)
0,05 0,10
(a.1)
1,5 1,0
0,00 0,02 0,04 0,06 0,08 (a.2)
3-1,0
0,02 (b.2)
0,05 0,10 (b.1)
Fig. 15. Experimental results, Case 3: Balanced distorted source voltages
Fig. 16,b.1 presents a voltage sags of two phases in three phase source voltages from t = 1:65 s to t = 2:15 s. This case is considered as one of the most spread sags in the grid networks. From Fig. 16,b.2, one can notice that, the enhanced algorithm gives coherent reference voltages to compensate that occurred on the grid and make it balanced sinusoidal as shown in Fig. 16,b.3.
To put the dynamic voltage restorer under more sever conditions a three phase voltage sag is considered from t = 2:54 s to t = 2:67 s in the third test as shown in Fig. 16,c.1. The DVR stills generate the wanted voltages as shown in Fig. 16,c.2, to compensate the occurred sag on the grid and ensure the balanced three phase voltages of the grid, Fig. 16,c.3.
(a.1)
tf 100 0 o c 0 0
■—wwww—
(a.2)
(a.3)
IA 100 0 O c 0 0
(b.1)
(b.2)
2,0 (b.3)
Fig. 16. Experimental results, DVR behavior under different conditions
(c.1)
(c.2)
(c.3)
0,15
2
200
100
-100
-100
-200
-200
200
ry -100
200
200
100
00
Conclusions.
Voltage sag is a crucial problem for industries, indeed, it introduce malfunction for costumer's equipments. Researchers have investigated numerous solutions to mitigate the harmful effect of voltage sag. Dynamic voltage restorer is one of the most famous solutions. In this paper, authors have introduced an enhanced algorithm based on synchronous reference frame to control a dynamic voltage restorer for voltage sags rejection. The presented algorithm is based on a Multi variable filter in order to synthesis unitary signals containing fundamental phase angle information involved in generating necessary voltages for compensating the occurred sags. The considered algorithm is tested under different conditions such as single phase sag, two phase sag and three phase sag, on the other hand, the Multi variable filter configuration is examined under the most sever conditions such as a total phase exclusion and in the case of a huge account of harmonic presence, where elimination of harmonics is not our case of study in this paper but to show the effectiveness of the proposed algorithm in synthesizing the unitary signals. The efficiency of the introduced method is validated by simulation and experimental results.
Conflict of interest. The authors declare that they have no conflicts of interest.
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Received 24.05.2021 Accepted 25.06.2021 Published 27.08.2021
Abdelfettah Boussaid , , Doctor of Electrical Engineering, Professor,
Seif El Islam Chelli 2, PhD Student,
Ahmed Lokmane Nemmour , Doctor of Electrical Engineering, Professor,
Abdelmalek Khezzar , Doctor of Electrical Engineering, Professor,
1 Institut des Sciences et des Techniques Appliquées, University Frères Mentouri Constantine 1, Algeria,
2 Laboratoire d'électrotechnique de Constantine, University Frères Mentouri Constantine 1, Algeria, e-mail: Abdlfettah.Boussaid@lec-umc.org (Corresponding author),
seif-elislam.chelli@lec-umc.org
Ahmed-Lokmane.Nemmour@lec-umc.org
abdelmalek.khezzar@lec-umc.org
How to cite this article:
Boussaid A., Chelli S.E.I., Nemmour A.L., Khezzar A. An effective control algorithm for dynamic voltage restorer under symmetrical and asymmetrical grid voltage conditions. Electrical Engineering & Electromechanics, 2021, no. 4, pp. 53-63. doi: https://doi.org/lQ.2Q998/2Q74-272X.2Q21.4.Q7.
