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47
SSBDDs and Double Topology for Multiple Fault
Reasoning
Raimund Ubar, Sergei Kostin, Jaan Raik
Department of Computer Engineering Tallinn University of Technology
Abstract — The paper presents a novel view on the Structurally Synthesized BDDs (SSBDD) as a model with inherent double topology for compact modeling of single faults and efficient reasoning of multiple faults. The nodes of SSBDDs represent lower level signal path topology in the original circuit, and the paths of SSBDD represent higher level topology of conditions to be processed during fault reasoning. The double topological view on SSBDDs allows to give easy explanation of the limitations of existing methods of multiple fault testing, and shows the ways how to avoid fault masking. A generalization of the test pair approach in a form of the concept of test groups is introduced for testing multiple faults.
Keywords: combinational circuits, binary decision diagrams, multiple fault testing, fault masking.
I. Introduction
Within the last two decades BDDs [1-3] have become state-of-the-art data structure in VLSI CAD for representation and manipulation of Boolean functions. Overviews about different types of BDDs can be found for example in [4,5].
Traditional use of BDDs has been functional, i.e the target has been to represent and manipulate the Boolean functions by BDDs as efficiently as possible. Less attention has been devoted to representing by BDDs the structural properties of logic circuits in form of mapping between the BDD nodes and the circuit implementation. This aspect was introduced in [6,7], where one-to-one mapping between the nodes of BDDs and signal paths in the circuit was introduced. These BDDs were initially called as alternative graphs [6,7], and later as structurally synthesized BDDs (sSbDD) [8]. The name SSBDD stresses the way how the BDDs are created from the gate-level network structure of logic circuits.
The mapping between the SSBDD nodes and the structure of the circuit can be regarded as the first level diagnostic topology inherent in SSBDDs, namely the topology of fault propagation paths in the circuit. Each node of SSBDD models different aspects related to a particular signal path in the original circuit, such as propagated signal waveforms, subsets of activated faults, timing characteristics like signal delays. These issues cannot be simulated explicitly with „classical^ BDDs, since the nodes of BDDs have only functional meaning and represent only the primary input variables [8,9].
Manuscript received July 27, 2012.
Raimund Ubar is with the Tallinn University of Technology, Department of Computer Engineering, Estonia, e-mail: raiub@ati.ttu.ee
Sergei Kostin is with the Tallinn University of Technology, Department of Computer Engineering, Estonia, e-mail: skostin@ati.ttu.ee
Jaan Raik is with the Tallinn University of Technology, Department of Computer Engineering, Estonia, e-mail: jaan. raik@ ati.ttu.ee
A problem that is still not solved in the field of test and fault diagnosis is how to manage fault masking and generate tests for multiple faults which may mask each other.
The graphical representation of SSBDDs can be regarded as the second level diagnostic topology, since each path in the SSBDD may model not only fault activation conditions for test generation purposes, but also potential masking conditions between the multiple faults in the circuit.
The double topology inherent in SSBDDs which is represented first, by the set of nodes, and second, by the set of paths in SSBDDs, allows to create efficient algorithms for multiple fault analysis, test generation and fault diagnosis, because of the straightforward and easily computable representation of very complex fault relationships.
In this paper we consider the use of SSBDDs for analyzing multiple suck-at faults (MSAF) considering in fact only single stuck-at-faults (SSAF). Most approaches to multiple fault test have tried to reduce the complexity of handling MSAF [10-12]. A totally different idea, which is based directly on the SSAF model only, involves two-pattern test approach [13-14] where test pairs were proposed to identify fault-free lines. In [15], the insufficiency of test pairs was shown to guarantee the detection of multiple faults. To overcome the deficiency of test pairs, a new method of test groups was elaborated [16-17]. The idea of test groups for identifying fault-free subcircuits in the circuit under test was introduced the first time in [16]. In [17], it was proven that a test group is robust regarding multiple faults, and is sufficient for detecting any non-redundant multiple fault in a combinational circuit.
In this paper we show the limitations of both, test pairs and the test groups, and show how to overcome these limitations by using the topology inherent in the nodes and paths of SSBDDs.
The rest of the paper is organized as follows. Section 2 explains the concept of SSBDD. In Section 3 we discuss the method of test pairs, and provide a counterexample to show the limits of this approach. Section 4 discusses the fault masking issues, and Section 5 presents the concept of test groups. In Section 6 we show the sufficiency of test groups for detecting multiple faults of any multiplicity using the topological view on SSBDDs. Section 7 provides some experimental results, and Section 8 concludes the paper.
II. Structurally Synthesized Binary Decision
Diagrams
Let us have a gate level combinational circuit with fanouts only at inputs. Consider the maximum fan-out free
region (FFR) of the circuit with inputs at the fan-out branches and fan-out free inputs. Let the number of the inputs of FFR be n. For such a tree-like sub-circuit we can create an SSBDD with n nodes by superposition of BDDs of gates in the circuit [6-9].
Example 1. In Fig. 1 we have a circuit with a FFR-module which can be represented by a Boolean expression:
У = *„(X21X3 V Х41*5 )(X61 V *7) V
V *22 (X12 X8 V X62 X9 )(X42 V X7 )
and as SSBDD in Fig.2. The literals with two indexes in the formula and in the SSBDD denote the branches of fan-out stems, and represent signal paths in the circuit. In this example, there are only two branches for each fanout, the second index 1 is for the upper branch in the circuit in Fig.1, and the second index 2 is for the lower branch. For instance, the bold signal path in Fig.1 is represented by the literal X12 in the formula and by the node x12 in the SSBDD in Fig.2.
Fig. 1. Combinational circuit with four faults
Fig. 2. SSBDD for the circuit in Fig. 1 with four faults
Every combinational circuit can be regarded as a network of modules, where each module represents an FFR of maximum size. This way of modeling of the circuit by SSBDDs allows to keep the complexity of the model (the total number of nodes in all graphs) linear to the number of gates in the circuit.
Definition 1. SSBDD model for a given circuit is a subset of SSBDDs, where each of them represents an FFR, and another subset of SSBDDs, where each of them contains a single node representing a primary fan-out input.
As a side effect of the synthesis of SSBDDs, we build up a strict one-to-one relationship between the nodes in SSBDDs and the signal paths in the modules (FFRs) of the circuit. Direct relation of nodes to signal paths allows to handle with SSBDDs easily such problems like fault modeling, fault collapsing, and fault masking.
Definition 2. Let us call the one-to-one mapping between the SSBDD nodes and the topology of signal paths in the original circuit as the first level diagnostic topological property of SSBDDs.
The first level topological property of SSBDDs allows a compact representation of a set of properties inherent to the circuit signal paths by a single property of the related SSBDD node. For example, all the 10 SAF along the signal path from x12 to y in the circuit in Fig.l are represented by only 2 SAF of the SSBDD node x12 in Fig.2.
The variables in the nodes of SSBDD, in general, may be inverted. They are inverted when the number of invertors on the corresponding signal path in the circuit is odd. The two terminal nodes of the SSBDD are labeled by Boolean constants #1 (truth) and #0 (false).
Logic simulation with SSBDDs. Tracing paths on an SSBDD can be interpreted as a procedure of calculating the value of the output variable y for the given input pattern. The procedure is carried out by traversing the nodes in SSBDD, depending on the values of the node variables at the given pattern. By convention, the value 1 of the node variable means the direction to the right from the node, and the value 0 of the node variable means the direction down. Calculation begins in the root node, and the procedure will terminate in one of the terminal nodes #1 or #0. The value of y will be determined by the constant in the terminal node where the procedure stops for the given input pattern.
Example 2. Consider again the circuit and SSBDD in Fig.l, and Fig.2. For the pattern 100111010 (123456789), a path (xll, x2l, x4l, x5, x6l, #l) in the SSBDD is traced (shown by bold lines in Fig. 2), which produces the output value y =l for the given pattern.
III. Topological diagnostic modeling with SSBDD
Let have an FFR-module of a circuit which implements a function y = fX) where X is the set of input variables of the module, and is represented by SSBDD with a set of nodes M. Let x(m)eX be the variable at the node meM, and let m0 and m1 be the neighbors of the node m for the assignments x(m) = 0 and x(m) = l, respectively.
Activation of SSBDD paths. Let Tt be a pattern applied at the moment t on the inputs X of the module. The edge (m,me) in SSBDD, where ee{0,l}, is called activated by Tt if x(m) = e. A path (m, n) is called activated by Tt if all the edges which form the path are activated.
To activate a path (m, n) means to assign by Tt the node variables along this path the proper values. path activation can be interpreted as a reverse task to SSBDD simulation.
Definition 3. Let us call the mapping between the paths (m0,#e) in SSBDD from the root node m0 to one of the terminal nodes #e, where e e{0,l}, and the set of input patterns which activate the path (m0,#e), as the second level diagnostic topological property of SSBDDs.
The second level topological property of SSBDDs allows not only a compact representation of the truth table
of the circuit, but also efficient test generation, fault simulation and straightforward reasoning of complex fault relationships like multiple fault masking.
Fig. 3. Topological view on testing of nodes on the SSBDD
Test generation. A test pattern Tt will detect a single stuck-at-fault (SSAF) x(m) = e, ee{0,l}, if it activates in the SSBDD three paths: a path (m0,m) from the root node to the node under test, two paths (m0, #0), (m1, #1) for fault-free and faulty cases, and satisfies the fault activation condition x(m) = e © 1.
Assume e = 1. To simulate the test experiment for Tt, generated for the fault x(m) = 1, first, the path (m0,m) will be traced up to the node m which will “serve as a switch”. If the fault is missing, the path (m0, #0) will be traced, and if the fault is present, the path (m1, #1) will be traced.
Note, that a test pattern Tt for a node fault x(m) = e detects single SAFs on all the lines of the signal path in the circuit, which is represented by the node m in SSBDD.
Example 3. Consider the fault x11 = 1 in the circuit of Fig.l, represented by the fault x(m) = x11 = 1 in the SSBDD in Fig.1. Since the node under test m and the root node are the same, m = m0, the first path (m0,m) is collapsed, and need not activation. To generate a test pattern Tt for x11 = 1, we have to activate two paths: (m0 ,#0) and (m1, #1), like (x22=0, #0), and (x21=0, x41=1, x5=1, x61=1, #1), respectively. For the node under test we take x11 = 0 which means that the expected value will be y = 0. Since the fault x11 = 1 is present, the path (x11,x21,x41,x5, x61,#1) will be traced when simulating the test experiment, and the value #1 in the terminal node will indicate the presence of fault.
Fault simulation of a test pattern Tt on the SSBDD is carried out by the following procedure:
(1) The path (m0,#e) where ee{0,1}, activated by the test pattern Tt will be determined.
(2) For each node me(m0,#e), its successor m*g(m0,#e), is determined, and the path (m*,#e*) from m* to a terminal #e* will be simulated; if e Ф e* then the fault of the node m is detectable by Tt , otherwise not.
Example 4. Consider the SSBDD in Fig.2. For the input pattern Tt = 100111010 (123456789), a path (x11, x21, x41, x5, x61, #1) in the SSBDD is activated, which produces e = 1. According to Step 2 we find that the nodes x11, x41, and x5 have all the same successor x22, and by simulation the path (x22,#e*) we find that e* = 0, which
means that the test pattern is able to detect the faults x11 = 0, x41 = 0, and x5 = 0, since e Ф e*. The fault x61 = 0 is as well detectable, since the activated path (x7, x22, #e*) gives as well e* = 0. It is easy to see that the fault x21 = 1 is not detectable since the activated path (x3, x41, x5, x61, #e*) produces the same result e* = 1 as in the case when the node x21 is correct.
Fault diagnosis. Let a test pattern Tt is carried out during diagnosis experiment. First, we relate to the test pattern Tt the set of faults R(T) = {x11 = 0, x41 = 0, x5 = 0, x61 = 0} detectable by Tt. This set of faults was calculated by fault simulation. We have now two possibilities:
(1) If the pattern Tt fails, we will suspect all the faults of R(T) as faulty. To have a better diagnostic resolution we have to carry out additional test patterns to prune the set of candidate faults as much as possible.
(2) If the pattern Tt passes, it would be logical to conclude that the faults of R(T) are not present. However, it is correct only in the case when it is assumed that the circuit may consist always only a single fault.
Example 5. Consider the circuit and SSBDD in Fig.1. Assume that the circuit contains four faults: R = {x11 = 1, x22 = 1, x42 = 0, x61 = 0}. Let us apply again to this faulty circuit the test pattern Tt = 100111010 (123456789). Since (x61 = 0) є R(T), we should expect that the test pattern will fail. However, the test will pass because the detectable fault (x61 = 0) є R(T) n R, is masked by the fault (x22 = 1) є R.
To manage potential fault masking during the test experiments, more advanced methods for test pattern generation and fault diagnosis should be used.
IV. Fault Masking in Digital Circuits
Consider again the combinational circuit in Fig.1 which contains four stuck-at faults: x11=1, x22=1, x42=0, and x61=0. All the faults are depicted also in SSBDD in Fig.2.
Example 6. Table I contains four test patterns targeting these faults (“target faults” in column 11) as single faults. All the four test patterns will pass and not detect the target faults because of circular masking by another fault (Fig.4).
Table I
Test patterns for selected faults in Fig.1
t Test patterns Tt Target faults Mask faults
x1 x2 x3 x4 x5 x6 x7 x8 x9
1 0 0 - 1 1 1 0 1 0 x11 = 1 x61 = 0
2 1 0 - 1 1 1 0 0 1 x61 = 0 x22 = 1
3 0 0 1 1 0 1 1 - 1 x22 = 1 x42 = 0
4 0 1 0 1 1 1 1 - 1 x42 = 0 x11 = 1
5 1 0 - 1 1 0 0 1 0 x22 = 1 0
5
x22 = 1 can be detected by T5
How to find this pattern?
Fig. 4. Four faults masking each other in a cycle
There exists however another test pattern T5 (in Table I and Fig. 4) which would be able to “break the masking cycle" by detecting the fault x22 = 1, one of the targeted four faults. The problem is how to find this pattern, or in general, how to find a test pattern for a given fault, which would be immune against masking by any possible combination of multiple faults.
To avoid fault masking, a method was proposed to use two patterns (test pairs) where the first pattern has the task to test the target fault, and the second pattern has the role of testing the possible masking faults [13,14]. The main idea of this concept is to conclude from the passed test pair the correctness of the wire xt under test, i.e. the absence of the both faults xt =0 and xt =1. Unfortunately, not always the test pairs are working as expected [15,16].
Table II
Test pairs for testing 4 paths in the circuit in Fig.1
t Test pairs TP t = {Tt, Tt+i} Target faults Test wires
Xi X2 X3 X4 X5 X6 X7 X8 X9
l 0 0 - i i i 0 l 0 X11 = 1 x11
2 i 0 - i i i 0 l 0 X6i = 0
3 i 0 - i i i 0 0 l О Ш * X61
4 i 0 - i i 0 0 0 l x22 = 1
5 0 0 i i 0 i i - l X22 = 1 x22
6 0 i i i 0 i i - l X42 = 0
7 0 i 0 i i i i - l О Ш * x42
8 0 i 0 0 i i i - l xll = 1
9 i 0 - i i i 0 l 0 X6i = 0 X61
10 i 0 - i i 0 0 l 0 x22 = 1
Example 7. Table II contains four test pairs targeting the same four faults as shown in Fig. 1 ("target faults" in column 11) by testing the corresponding wires xn, x22, x42, and x6i for both faults SAF-1 and SAF-0. None of the test pairs will detect any of the four faults (see Fig. 5), all 8 patterns will pass returning the message that all four wires are working correctly, which however is not the case. The first test pair TP1(T1,T2) consisting of test patterns T1 and T2 is not able to prove the correctness of the wire x11: the first pattern T1 targeting the fault x11 = 1 will pass because of the masking fault x61 = 0 whereas the second pattern T2 which targets the masking fault x61 = 0 will pass because of another masking fault x22 = 1. The test pair fails to prove the correctness of the wire under test.
In a similar way the test pair TP3 (T3,T4) will fail in testing the wire x61, the test pair TP5 (T5,T6) will fail in testing the wire x22, and the test pair TP7 (T7,T8) will fail in testing the wire x42. The cycle of masking closes.
There is however a test pair TP9 (T9,T10) shown in Table II and in Fig. 5, which would be able to "break the masking cycle" by testing the wire x22, and detecting the fault x22 = 1, one of the four faults in Fig.l. Note, the test pattern Tl0 is the same as the test pattern T5 in Table I. The problem is how to find the test pair TP9 involving the pattern Tl0, or in general, how to find a test pair for a given wire, which would be immune against masking by any possible combination of multiple faults.
V. The test group concept
The answer lays in a solution based on constructing of test groups instead of test pairs [16,17]. A possible solution for this example is presented in Table III as a set of three test patterns which are targeting to test the wires xll and x6l, being immune to the masking fault x22 = l. The first pattern T0 will pass and not detect the fault x6l = 0, because of the masking fault x22 = l. The second pattern Tl will fail as well in detecting the fault xll = l because of the masking fault x6l = 0. However, the third pattern T3 will detect x22 = l and break in this way the cycle of masking.
Cycle of fault masking
TPt(Tt,T8)
Solution:
Test Group TG (including Тю)
proves the correctness of lines x^ and x61
x,,= 1
TP,(T„T2)
x61 = 0 TP5(T5,T6)
x42 = 0
tTP3(T3,T4)
x22 = 1
x22 = 1 can be detected by Тю, or by TP9(T9,T1q)
How to find this Test Pair?
I
Test Pair TPq(Tq, Т10)
Fig. 5. Breaking the fault masking cycle
Table III
A TEST GROUP WHICH DETECTS ALL THE FOUR FAULTS IN FlG.l
t Test group TG = {Tt,Tt+i,Tt+2} Test faults Mask faults
Xi X2 X3 X4 X5 X6 X7 X8 X9
0 1 0 l l l 1 0 l 0 = 0 X22 = l
1 0 0 l l l 1 0 l 0 Xll = l X6i = 0
2 1 0 l l l 0 0 l 0 X6i = l 0
Let us describe shortly the main idea of test groups [14].
Definition 4. Let us introduce the terms: test group TG = {T0,Tl...,Tk}, main pattern T0eTG of the test group, and subset of co-patterns TG* = {Tl...,Tk} c TG of the test group. The main pattern T0 activates a main path L0 = (m0, #e) in a ssBDD from the root node m0 to one of the terminal nodes #e, ee{0,l}, and each co-pattern Tt activates a co-path Lt = (m0, #(—e)) through the node mt є L0, so that all Tt will differ from T0 only in the value of x(mi).
The test group TG has the target to test a subset of nodes MTG ={ml,...,mk} c L0, where at T0 , for all i = l,...,k: x(m) = e. T0 has the target to test all the faults x(m) = —e, mt є MTG, and each co-pattern Tt has the target to test the fault x(mi) = e. The main condition of TG is that all the variables which do not belong to MTG ={ml,... ,mk}cL0 should keep the same value for all the patterns in TG.
Example 8. In Table III, a test group TG = (T0,Tl,T2) is depicted. Let D0lllD0l0 (123456789) be a symbolic representation of the test group where D = l in T0, and for other Tt, only one of the D-s is equal to 0.
The main pattern T0 activates the main path L0= (xll,x2l,x4l, x5,x6l,#l) shown by bold edges in Fig.2. TG has the target to test the subset of nodes MTG = {xll ,x6l} in the SSBDD, particularly, xll = 0, and x6l = 0 by T0 , xll = l by Tl, and x6l = l by T2. Note, the values of the other
variables x2, x3, x4, x5, x7, x8, and x9, not belonging to the main path L0, remain unchanged for TG.
According to the definition of SSBDD, this test group tests all the SSAF on the signal paths starting on the inputs of the FFR xu and x61 up to the output y of the circuit. This conclusion results from the first level diagnostic topology inherent in SSBDDs
It is easy to realize that the test pair is a special case of the test group, where | MTG | = 1.
The problem is how to generate test groups to avoid any fault masking in the circuit for arbitrary case of multiple faults. To answer this question, let us discuss the role and meaning of the second level diagnostic topology represented by the paths structures in SSBDDs.
VI. Topological view on fault masking
Definition 5. Introduce a term activated masking path. Note that the role of each co-pattern Tt є TG of the test group TG is to keep the masking paths, which may corrupt the result of the main pattern T0, activated. Activation of the masking path is the necessary and sufficient condition for detecting the faults targeted by the test group.
Consider a skeleton of SSBDD in Fig.6a with highlighted root node m0, two terminal nodes #0, #1, and two faulty nodes a = 0, c = 1. The dotted lines represent activated paths during a test pair TP = {T0,T1}which has the goal to test the correctness of the node a. T0 is for activating the correct path L1 = (m0, a, #1) to detect the fault a = 0 with expected test result #1. If the fault is present, then instead of L1, a “faulty” path L0 = (a =0, c, #0) should be activated with faulty result #0.
In case of another fault c = 1 on L0, a masking path LM = (a, c, #1) will be activated, and a = 0 will be not detected by T0. However, at T the masking path LM remains activated because of the fault c = 1, and the wrong test result #1 will indicate the presence of a masking fault in the circuit. It means that the multiple fault {a = 0, c = 1} will be detected.
© ©
<5^-©-1-©
LM © // LM L0 LM
L0 ! db
a) b)
Fig. 6. Comparison of a test pair with a test group
Both patterns of TP = {T0,Ti} will pass and not detect this multiple fault if the masking path LM will contain a node labeled by the same variable as the tested node. For example, in Fig.6b, both Li and LM contain a node with the same variable a, which is the reason why the test pair is not sufficient for detecting the multiple fault {a = 0, c = 1}. In this case the co-pattern T of the test pair TP is not able to keep the masking path activated.
To overcome the problem, it would be necessary and also sufficient to include into the set of nodes to be tested by a test group at least one node which is labeled by a
variable not labeling any node on LM. For example, in Fig.6b, it would be sufficient for detecting the multiple fault {a = 0, c= 1} to generate a test group for testing the nodes {a,b}.
Theorem. A test group TG for a subset of nodes MTG is robust with respect to any multiple stuck-at-faults in the circuit if for each possible masking path LM, there exists a node mєMTG, so that no node on the LM will have the same variable x(m).
Proof. Suppose, the main test pattern T^ TG ’ does not detect a fault A because another fault B activates a masking path LM. According to definition of test groups, each co-pattern TiєTG’ differs from T0 in a value of a single variable x(mi) where m^MTG. Suppose T is testing the node mi labeled by the variable x(m), and the masking path LM does not contain a node labeled by the same variable x(m). In this case, LM remains activated during Ti and hence, provides the same result for Tt as it was for T0. This means that the pattern Ti will detect the masking fault B . The same considerations hold for every possible masking path. ■
From Theorem, a straightforward algorithm results for tracing all the possible masking paths for the given test group to check if the conditions of Theorem are satisfied. If a path will be found where the conditions are not satisfied, the test group should be extended by additional variable which corresponds to the definition of the test group and satisfies the conditions of Theorem. If the needed extension will be not possible, the masking path is redundant [17], and the corresponding MSAF is redundant as well.
Fig. 7. Topological view on the fault masking mechanism
Example 9. In Fig.7, a topological view is presented, based on a skeleton of SSBDD, on different possibilities of fault masking. L0 represent a main path as the basis of a test group construction. Let the test group TG targets the nodes MTG = {a,b,c}. T^TGwill not detect the fault a = 0 because of another SAF-1 fault. There may be arbitrary combinations of masking faults in the circuit denoted by =1. By dotted lines, possible masking paths are depicted. As we see, for each such a path LM, there exists always a node m є MTG with a variable x(m) which is missing on the particular LM. Hence, the test group satisfies the conditions of Theorem
The concept of test groups was discussed here for single-SSBDD models. In case of a system of more than one SSBDD, we have to either reduce the model by superposition of SSBDDs [8] to the single-SSBDD case
for each output of the circuit, or to use a hierarchical approach to handle the whole system of SSBDDs.
The main goal of test groups is to identify or prove the correctness of a subset of nodes in SSbDd. The knowledge about the nodes identified already as correct allows to generate smaller partial test groups to ease test generation, and the known correct nodes can be dropped from analysis. The method allows creating a sequential procedure of fault diagnosis by extending step by step the fault free core in the circuit at any present multiple fault.
VII. Experimental data
In Table IV, experimental data of extending a given SSAF test to MSAF test are presented for ISCAS’85 circuits. Only the test groups with the length of three were considered.
From the SSAF test, all the main patterns were extracted and extended by two co-patterns if they were missing in the original test set. The group cover shows the percentage of main patterns successfully extended up to the test groups. On one hand, the cover demonstrates the level of feasibility of test group generation. On the other hand, it characterizes the robustness of the MSAF test regarding the multiple faults. The columns 3 and 4 show the number of patterns in the SSAF test and in the test set which was composed from the test pattern groups, respectively. The fair comparison between SSAF and MSAF test lengths could not be done in the present research, since the test groups for different outputs were not merged.
Table IV
Experimental data of generating test groups
Circ. Gates SSAF test # MSAF test # Group cover%
c432 275 53 314 82,91
c499 683 86 482 67,2
c880 429 84 546 99,8
c1355 579 86 514 65,6
c1908 776 123 621 96,3
c2670 1192 103 820 76,3
c3540 1514 148 995 80,3
c5315 2240 104 1523 91,8
c6288 2480 22 465 98,1
c7552 3163 202 1863 87,8
VIII. Conclusions
In this paper we presented a novel fault diagnosis oriented view on the SSBDD model as the double topology inherent in SSBDDs. The first level topology refers to signal paths in the original circuit which are mapped to the nodes of SSBDDs, and the second level topology is related to the SSBDD paths structure and refers to the conditions to be processed during fault simulation, test generation and managing fault masking issues.
We presented the idea of generating test groups for testing multiple faults, based on the topological concept of SSBDDs. Differently from the known approaches, we don’t target the faults as test objectives. Instead of that, the goal is to verify by test groups the correctness of a
selected part of a circuit, represented by a group of nodes in SSBDD.
The main power of the method is to facilitate fault diagnosis in the presence of multiple faults. The knowledge about identified correct parts of the circuit allows to extend step by step the core of the circuit proved as correct.
Experimental results showed high feasibility of generating test groups by achieved high percentages of the group coverage. The coverage can be further increased by using the knowledge about the correct parts of the circuit during testing.
Acknowledgement: The work has been supported by the project FP7-ICT-2009-4-248613 DIAMOND and by EU through the European Regional Development Fund.
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