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Matrix Implementation of Moore FSM with Encoding of Collections of Microoperations
A. Barkalov, L. Titarenko, O. Hebda, K. Soldatov
Abstract — The method is proposed for reduction of hardware amount in logic circuit of Moore finite state machine. The method is oriented on customized matrix technology. It is based on representation of the next state code as a concatenation of code for class of collection of microoperations and code of the vertex. Such an approach allows elimination of dependence among states and microoperations. As a result, both circuits for generation of input memory functions and microoperations are optimized. An example of the proposed method application is given.
Index Terms — Customized matrices, graph-scheme of algorithm, logic circuit, Moore FSM, pseudoequivalent states.
I. Introduction
The model of Moore finite state machine (FSM) [1] is often used during the digital control systems realization [2, 3]. The development of microelectronics has led to appearance of different programmable logic devices [4], used for implementing FSM circuits. But in the case of mass production, they use ASIC (Application-Specified Integrated Circuits) [6]. In this case the circuit is implemented using customized matrices using the principle of distributed logic [7].
One of the important problems of FSM synthesis with ASIC is decrease of the chip area occupied by its logic circuit. One of the ways to solve this problem is optimal coding of FSM [2]. However this approach does not allow optimization of the circuit generated output signals. In this work some new optimization method is proposed. It is based on representation of the next state code as a concatenation of codes for class of pseudoequivalent states and vertex where this collection is generated. Such an approach allows reducing of hardware amount in both parts
Manuscript received October 9, 2009. Matrix Implementation of Moore FSM with Encoding of Collections of Microoperations.
A. Barkalov is with the Institute of Computer Engineering and Electronics, Zielona Gora, Poland (corresponding author to provide phone: 0-683282693; e-mail: A.Barkalov@iie.uz.zgora.pl).
L. Titarenko is with the Institute of Computer Engineering and Electronics, Zielona Gora, Poland (e-mail: L.Titarenko@iie.uz.zgora.pl).
O. Hebda is with the Institute of Computer Engineering and Electronics, Zielona Gora, Poland (e-mail: O.Shapoval@iie.uz.zgora.pl).
K. Soldatov is with the Institute of Computer Engineering Donetsk National Technical University, Donetsk, Ukraine (e-mail: k.soldatov@cs.donntu.donetsk.ua).
of FSM circuits and does not lead to speed loss. A control algorithm to be implemented is represented by the graph-scheme of algorithms [1].
II. The general Aspects and the Basic Idea of Proposed Method
Let Moore FSM be represented by the structure table (ST) with columns [1]: am , K(am), as, K(as), Xh , ФА , h . Here am is an initial state of FSM; K(am) is a code of state am e A of capacity R = |"log2 M ], to code the states the internal variables from the set T = {T1,..,Tr} are used; as, K (as), are a state of transition and its code respectively; Xh is an input, which determines the transition (am, as}, and equal to conjunction of some elements (or their complements) of a logic conditions set X = {x1,..,xl} ; фh is a set of input memory functions for
flip-flops of FSM memory, which are equal to 1 for memory switching from K (am) to K (as),
Фh £Ф = {ф1- ^r}; h = 1, ..., Я is a number of transition. In the column am a set of microoperations Yq is written, which is generated in the state am e A , where Yq c Y = {yi,..,yN}, q = 1,...,Q . This table is a basis to
form the system of functions
Ф=Ф(Т, X), (1)
Y = Y (T ) , (2)
which determines an FSM logic circuit. Systems (1)-(2) describe the matrix model of Moore FSM t/j, shown in Fig. 1.
Fig. 1. Matrix implementation of FSM U1
In FSM U the conjunctive matrix Mx implements the
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system of terms F = {fy,...,FH}; the disjunctive matrix M 2 implements the system (1); the conjunctive matrix M3 implements the terms Am (m = 1,...,M) corresponding to FSM states; the disjunctive matrix M4 implements functions (2). The register RG keeps state codes. The matrices M1 and M2 forms the block of input memory functions (BIMF) whereas the matrices M3 and M 4 the block of microoperations (BMO). The area of BIMF can be decreased using the approach of optimal state encoding [8]. It permits to decrease the number of terms in system (1) up to H0, where H0 is the number of transitions for equivalent Mealy FSM. The area of BMO can be decreased due to refined state encoding [9]. It is possible some outcome of encoding, when the matrix M 4 is absent. But these methods cannot be used together. In this article the method is proposed permitting mutual area decrease for both blocks of FSM.
One of Moore FSM features is existence of pseudoequivalent states [2], which are the states with the same transitions by the effect of the same inputs. Such states correspond to the control algorithm operator vertices [1], outputs of which are connected with an input of the same vertex.
Let Пa = [B1,.,BI} be a partition of a set A on classes of pseudoequivalent states. Let us code classes Bi e Па by binary codes K (Bt) having Rb bits, where
Rb =Tlog2 11 (3)
Let initial GSA Г include Q different collections of microoperations (СМО) Yq c Y. Let us code set Yq with binary code K(Yq) having Ry bits, where
Ry =Tlog2 Ql (4)
Let E1 = {t>1,...,bD} be a set of operator vertices from GSA Г . Let us use the following relation a on this set E1
biabj -o Y (bi) = Y (bj). (5)
In (5), the symbols Y(bi),Y (bj) c Y stand for collections of MO from vertices bt and bq (i, j e{1,...,D}).The relation a determines the partition Па = {Cj,...,C^}. Let us encode each vertex bq e Cj by the binary code K (bq) having
Ra=Tlog2 G\ (6)
bits. In (6), G = max(|Cj,...,|c^|). Let us use variables zr e Zj for this encoding, where |zj = Ra . In this case, the code for state am e A can be represented as:
K (am) = K (Yq )* K (bq), (7)
where bq e Ej is the operator vertex marked by state
am e A , Yq = Y(bq), and * is the sign of concatenation.
Let us construct the system
B = B(A), (8)
which describes the dependence among the classes Bi e Пa from the states am e A . Each function Bi e B is represented as the following
Bt = VCmAm (i = 1,..., I), (9)
i=1
where the symbol Cim stands for Boolean variable equal to 1, am e Bi. The proposed matrix implementation of Moore FSM U2 is shown in Fig. 2.
Fig. 2. Matrix implementation of FSM U 2
In FSM U 2, the matrix M 5 implements the system of terms F0 corresponding to rows of transformed table of transitions and depending on logical conditions xi e X and additional variables Tr e т , used for encoding the classes Bi ena , where|т| = Rb. The matrix M6 implements the input memory functions
Фо =Фо(т, X), (10)
The system (10) includes Ry + Ra functions; it is the number of flip-flops from RG. The matrix M 7 implements terms Yo , entering the system yn e Y and depending from variables zr e Z, where |z| = Ry . The matrix M8 implements functions yn e Y, depending on terms Aq e Yo . The matrix M9 implements the terms Ao from (9), whereas the matrix Mw functions тг e т, used for encoding classes Bi e Пa , where |т| = Rb.
Matrices M5 and M6 form the block BIMF, the matrices M7 and M8 form the block BMO implementing the functions
Y = Y (Z). (11)
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Matrices M9 and M10 form the block of code transformer (BCT) generating functions
т = т( z, Z1). (12)
There are some positive features in the proposed method. Now codes of collections of microoperations do not depend on state codes. It allows encoding of collections Yq c Y minimizing the area of BMO. The number of rows
in the table of transitions for FSM U 2 is always equal to H0 . It allows such their encoding that diminishes the area occupied by BIMF. As it was mentioned, it is enough
Ra =[log2 M1 (13)
variables for state encoding in case of FSM U. The main drawback of U2 is increase of the number of inputs for BIMF if the following condition is true:
Ry + Ra > Ra . (14)
Besides, the model U2 includes the block BCT, which requires some area of the chip. But these drawbacks are compensated by area decrease for blocks BIMF and BMO in comparison with the model U1 .
III. Proposed Synthesis Method for Moore FSM
In this work a method of Moore FSM U 2 synthesis using a GSA Г is proposed. The method includes the next stages:
1. Marking of the GSA Г and creation of the state set A .
2. Partition of the set A on classes of pseudoequivalent states.
3. Coding of microoperation collections Yq c Y .
4. Construction of the partition Па and encoding of operator vertices bq e E .
5. Encoding the classes Bt e Пa .
6. Construction of transformed table of transitions.
7. Construction of system (12) by the table of BCT.
8. Implementation of matrices M5 - Mw .
For the first step implementation the known method [1] is used, when every operator vertex is marked by a unique state. The second step is trivially done by the use of pseudoequivalent states’ definition [2]. Remind, that states am, as e A are named pseudoequivalent, if marked by them operator vertices of GSA are connected with the input of the same vertex.
The main goal of the third step is maximum decrease for the number of terms in system Y0 . In the best case, each microoperation yn e Y is represented by a single term and the matrix M 8 is absent [1]. The fourth step is executed on the base of (5). The codes of states am e A are determined using the formula (7). Classes Bt e Пa are encoded in such a manner that the number of terms in (12) is maximally
decreased. It is reduced to the well-known task of symbolic encoding [3].
The transformed table of transitions includes the columns Bj, K (В,), as, K(as), Xk, Ф^, h . Here Фк c Ф0 is a
collection of input memory functions equal to 1 to write the code K (as) into the register; h = 1,..., Ho is the number of transition. The table of BCT includes the columns am , K(am), Вi, K(Вi), тт, m . Here Tm c т is the collection of variables equal to 1 into the code K(В,) from the m -th line of the table, where m = 1,.,M. The last step is discussed in the proposed example.
IV. Example of Application for Proposed Method Let the symbol U, (Гу) means that the GSA Гу is interpreted by the model Ui (i = 1,2). Let us discuss the example of design for Moore FSM U2(Ц), where GSA Г1 is shown in Fig. 3.
Fig. 3. Initial graph-scheme of algorithm
It can be found from GSA Г1, that A = {aj,...,a8}, M = 8, and Ra = 3. There is the partition
Пл = {Вь..., B4}, where В = {a!}, B2 = {a2, a3, a,^}, B3 = {a5, a6}, B4 = {a7, a8} . It gives us I = 4, Rb = 2, т = {т1, T2}. There are five different collections of microoperations in GSA Г1 : Y1 = 0, Y2 = {y1, y2},
Y3 = {y3} , Y4 = {y4} , Y5 = {y1,y3} . To encode them, it is enough Ry = 3 variables from the set Z = {z1, z2, z3}. Let us encode the collections Yq c Y as it is shown in Fig. 4.
Z
Z1Z2 00 01 11 10
0 Y1 * Y4 Y2
1 * * Y3 y5
Fig. 4. Codes of collections of microoperations U 2(Г[)
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The following system of equations can be obtained using Fig. 3 and Fig.4:
yi = Y2 vY5 = z2z3 = A1;
y2 = Y2 = z1z2 z3 = A2; y3 = Y3 v Y5 = z1 = A3; У4 = Y4 = z1z3 =A4;
The partition Па includes four classes: Q = b Й4,Й7}, C2 = {b^}, C3 = {£3,^5}, c4 = {b5}. It gives G = 3, Ra = 2, Zi = {z4, z5} . There is the following system (8) in our example:
Bi = Ai; B2 = A2 v A3 v A4;
1 1 2 2 3 4 (16) B3 = A5 v Аб; B4 = A7 v A8.
Let us encode the vertices bq e E1 in such a manner that
4 1
the state codes (7) are determined from Fig.5.
4Z1Z Zs000 001 011 010 110 111 101 100
00 a1 * aq a2 * as * *
01 * * * a5 a6 * * *
11 * * * * * * * *
10 * * a8 ay * * * *
Fig. 5. State codes for Moore FSM U2 (Ц )
The following codes can be found from the Karnaugh map (Fig. 5):
B1 = z2; B2 = z2 z4 z5; (17)
B3 = z5; B4 = z4.
Let us encode the classes B, e Па in the following manner K (B1) = 01, K (B2) = 00, K (B3) = 10,
K(B4) = 11. The following system can be derived from these codes:
T = B3 v B4 = z5 v z4;
T2 = B1 V B4 = z2 V z4.
(18)
The system (18) determines the block BCT, where the matrix M9 is absent.
Let us construct the system of generalized formulae of transitions for GSA Г1:
B1 — X1«2 v X1X2»3 v X1 X2a4;
B2 — X3X2a5 v X3 X2«6 v X3X4a7 v X3 X4«8; (19)
B3 —— a2; B4 —^ a1.
This system together with state codes from Fig. 5 leads to the transformed table of transitions for FSM U2(Ц), having H 0 = 9 lines (Table 1).
tableI
Transformed Table of Transitions for FSM U2(Ц)
Bi K (B,) as K (as ) Xh Ф h h
a2 01000 X1 D2 1
B1 01 a3 11100 X1X 2 D1D 2 D3 2
a4 01100 X1X 2 D2 D3 3
a5 01001 X3X2 D2 D5 4
B 2 00 a6 11001 X3 X2 D1D2 D5 5
a7 01010 X 3 X4 D2 D4 6
a8 01110 X3 X4 D2D3D4 7
B3 10 a2 01000 1 D2 8
B 4 11 a1 00000 1 - 9
This table is used to derive the system (10). For example, the following functions can be found from Table 1:
D1 = F2 v F5 =t1t2 x1x2 vt1t2x3 x2 ; D2 = F2 V... V F8;
D3 = F2 v F3 v F7; D4 = F6 v F7; D5 = F4 v F5. In the case of matrix implementation, there is no need in minimizing these functions. The table for BCT is absent on our example because the system (18) determines the functions (12). Let us find the areas for matrices M 5 -M10 , determined as the product for the numbers of inputs and outputs of the matrix. From system of functions we can find the following areas of matrices: S (M5) = 2(4 + 2) *9 = 108, S (M6) = 9*5 = 45,
S (M7, M8) = 5*4 = 20 and S (M9, M10) = 3*2 = 6. Thus, it is necessary 179 area units [1] to implement the logic circuit of Moore FSM U2(r1). It can be found for FSM U1(r1) that H = 19, S(M1) = 2(4 + 3)*19 = 166,
S(M2) = 19*3 = 57, S(M3) = 2*3*7 = 42 and
S(M4) = 7*4 = 28. It means that logic circuit of FSM ^(Ц) occupies 293 area units. Besides, the circuit of ^(Ц) has 4 levels of logic, whereas the circuit for U2 (Г1) only three (because functions т and Y are generated in the same time). Thus, application of proposed method for encoding of collections of microoperations with state code presentation in the form (7) allows area decrease for 1,7 times Moore FSM.
V. Conclusion
The proposed method of state code presentation targets on area decrease under implementation of Moore FSM logic circuit with customized matrices. This approach allows decreasing the number of terms in the system of input memory functions up to corresponding value of the equivalent Mealy FSM. Besides, this method permits decreasing the number of terms in the system of microoperations due to the lack of dependence among the
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state codes and codes of collections of microoperations.
Investigation for effectiveness of proposed method was conducted on the standard examples [10]. It shows that the proposed method permits to decrease the average chip area occupied by FSM circuit up to 52% in comparison with the standard FSM implementation. In the same time, it was the increase for FSM performance in 86% of examples. The further direction of our research is application of proposed method for case of FPGA.
References
[1] Baranov S., Logic Synthesis for Control Automata, Kluwer Academic Publishers, Boston, 1994.
[2] A. Barkalov, L. Titarenko, Logic Synthesis for FSM-Based Control Units. Springer - Berlin Verlag Heidelberg, Lectures Notes in Electrical Engineering, 2009, №53.
[3] DeMicheli G. Synthesis and Optimization of Digital Circuits, McGraw-Hill, NY, 1994.
[4] Maxfield C. The Design Warrior's Guide to FPGAs, Elseveir, Amsterdam, 2004.
[5] Smith M. Application-Specific Integrated Circuits, Addison-Wesley, Boston, 1997.
[6] Nababi Z. Embedded Core Design with FPGA, McGraw-Hill, NY, 2008.
[7] Yang S. Logic Synthesis and Optimization Benchmarks user guide. Technical report, №1991 - IWLS-UG-Saryang.-Microelectronics center of North Carolina.
Prof. dr hab. inz. Alexander BARKALOV, prof. UZ. Prof. Alexander A. Barkalov worked in Donetsk National Technical University (DNTU) from 1976 till 1996 as a tutor . He cooperated actively with Kiev Institute of Cybernetics (IC) named after Victor Glushkov. He got his degree of doctor of technical sciences (Informatics) in 1995 from IC. From 1996 till 2003 he worked as a professor of DNTU. From 2003 he has been working as a professor on Department of Electrotechnics, Informatics and Telecommunications of University of Zielona Gora. The area of his scientific activity is design methods for control units implemented with FPGA, CPLD, and ASIC.
Dr hab. inz. Larysa TITARENKO, prof. UZ. Prof. Larysa Titarenko has got her degree of doctor of technical sciences (Telecommunications) in 2005 from Kharkov National University of Radioelectronics (KNURE). Till September, 2003 she worked as a professor of KNURE. From 2005 she has been working as a professor on Department of Electrotechnics, Informatics and Telecommunications of University of Zielona Gora. The area of her scientific activity is design methods for control units implemented with FPGA, CPLD, and ASIC, as well as their application in telecommunications.
MA Olena Hebda. MA Olena Hebda studied at National aerospace university 'Kharkiv Aviation Institute' from 2003 till 2009 and has received higher education on speciality "Biotechnical and Medical Apparatuses and Systems" and qualification of the research engineer (electronics, telecommunications). In 2009 she has started PhD study on Department of Electro technics, Informatics and Telecommunications of University of Zielona Gora. The area of her scientific activity is design methods for control units implemented with FPGA, CPLD, and ASIC.
MA Kirill Soldatov. MA Kirill Soldatov studied at Donetsk National Technical University (DNTU) from 200 till 2010 and has received higher education on speciality “Computer systems and networks”. In 2010 he has started PhD study on the chair of computer engineering of DNTU. The area of his scientific activity is design methods for control units implemented with FPGA, CPLD, and ASIC.
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